Datasheet LT3437 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | High Voltage 500mA, 200kHz Step-Down Switching Regulator with 100µA Quiescent Current |
| 页数 / 页 | 28 / 9 — PI FU CTIO S (DD/FE). BIAS (Pin 6/Pin 10):. SYNC (Pin 9/Pin 14):. VC (Pin … |
| 文件格式/大小 | PDF / 573 Kb |
| 文件语言 | 英语 |
PI FU CTIO S (DD/FE). BIAS (Pin 6/Pin 10):. SYNC (Pin 9/Pin 14):. VC (Pin 7/Pin 11):. SHDN (Pin 10/Pin 15):. FB (Pin 8/Pin 12):
该数据表的模型线
文件文字版本
LT3437
U U U PI FU CTIO S (DD/FE) BIAS (Pin 6/Pin 10):
The BIAS pin is used to improve pin drops below 0.9V, switching frequency is reduced, the efficiency when operating at higher input voltages and SYNC function is disabled and output ramp rate control is light load current. Connecting this pin to the regulated enabled via the CSS pin. See the Feedback section in output voltage forces most of the internal circuitry to draw Applications Information for details. its operating current from the output voltage rather than
SYNC (Pin 9/Pin 14):
The SYNC pin is used to synchronize the input supply. This architecture increases efficiency the internal oscillator to an external signal. It is directly especially when the input voltage is much higher than the logic compatible and can be driven with any signal be- output. Minimum output voltage setting for this mode of tween 25% and 75% duty cycle. The synchronizing range operation is typically 2.7V. is equal to maximum initial operating frequency up to
VC (Pin 7/Pin 11):
The VC pin is the output of the error 700kHz. When the voltage on the FB pin is below 0.9V the amplifier and the input of the peak switch current comparator. SYNC function is disabled. When a synchronization signal It is normally used for frequency compensation, but can also or logic-level high is present at the SYNC pin, Burst Mode serve as a current clamp or control loop override. VC sits at operation is disabled. See the synchronizing section in about 0.45V for light loads and 1.5V at maximum load. Applications Information for details. During the sleep portion of Burst Mode operation, the VC
SHDN (Pin 10/Pin 15):
The SHDN pin is used to turn off the pin is held at a voltage slightly below the burst threshold for regulator and to reduce input current to less than 1µA. The better transient response. Driving the VC pin to ground SHDN pin requires a voltage above 1.3V with a typical source will disable switching and place the IC into sleep mode. current of 5µA to take the IC out of the shutdown state.
FB (Pin 8/Pin 12):
The feedback pin is used to determine
Exposed Pad (Pin 11/Pin 17):
Ground. Must be soldered the output voltage using an external voltage divider from to the PCB. the output that generates 1.25V at the FB pin. When the FB 3437fc 9
U U U PI FU CTIO S (DD/FE) BIAS (Pin 6/Pin 10):
The BIAS pin is used to improve pin drops below 0.9V, switching frequency is reduced, the efficiency when operating at higher input voltages and SYNC function is disabled and output ramp rate control is light load current. Connecting this pin to the regulated enabled via the CSS pin. See the Feedback section in output voltage forces most of the internal circuitry to draw Applications Information for details. its operating current from the output voltage rather than
SYNC (Pin 9/Pin 14):
The SYNC pin is used to synchronize the input supply. This architecture increases efficiency the internal oscillator to an external signal. It is directly especially when the input voltage is much higher than the logic compatible and can be driven with any signal be- output. Minimum output voltage setting for this mode of tween 25% and 75% duty cycle. The synchronizing range operation is typically 2.7V. is equal to maximum initial operating frequency up to
VC (Pin 7/Pin 11):
The VC pin is the output of the error 700kHz. When the voltage on the FB pin is below 0.9V the amplifier and the input of the peak switch current comparator. SYNC function is disabled. When a synchronization signal It is normally used for frequency compensation, but can also or logic-level high is present at the SYNC pin, Burst Mode serve as a current clamp or control loop override. VC sits at operation is disabled. See the synchronizing section in about 0.45V for light loads and 1.5V at maximum load. Applications Information for details. During the sleep portion of Burst Mode operation, the VC
SHDN (Pin 10/Pin 15):
The SHDN pin is used to turn off the pin is held at a voltage slightly below the burst threshold for regulator and to reduce input current to less than 1µA. The better transient response. Driving the VC pin to ground SHDN pin requires a voltage above 1.3V with a typical source will disable switching and place the IC into sleep mode. current of 5µA to take the IC out of the shutdown state.
FB (Pin 8/Pin 12):
The feedback pin is used to determine
Exposed Pad (Pin 11/Pin 17):
Ground. Must be soldered the output voltage using an external voltage divider from to the PCB. the output that generates 1.25V at the FB pin. When the FB 3437fc 9