Datasheet LT3434 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | High Voltage 3A, 200kHz Step-Down Switching Regulator with 100µA Quiescent Current |
| 页数 / 页 | 24 / 6 — TYPICAL PERFOR A CE CHARACTERISTICS. 3.3V Dropout Operation. 5V Dropout … |
| 文件格式/大小 | PDF / 418 Kb |
| 文件语言 | 英语 |
TYPICAL PERFOR A CE CHARACTERISTICS. 3.3V Dropout Operation. 5V Dropout Operation. Burst Mode Operation
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LT3434
W U TYPICAL PERFOR A CE CHARACTERISTICS 3.3V Dropout Operation 5V Dropout Operation Burst Mode Operation
4.0 6 VOUT = 3.3V VOUT = 5V 3.5 BOOST DIODE = DIODES INC B1100 BOOST DIODE = DIODES INC B1100 5 VOUT 50mV/DIV 3.0 4 2.5 LOAD CURRENT LOAD CURRENT 0.25A 2.0 0.25A 3 LOAD CURRENT LOAD CURRENT 1.5 2.5A 2.5A IOUT 2 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 500mA/DIV 1.0 1 V 0.5 IN = 12V 5ms/DIV 3434 G14 VOUT = 3.3V IQ = 100µA 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 1 2 3 4 5 6 INPUT VOLTAGE (V) INPUT VOLTAGE (V) 3434 G24 3434 G25
Burst Mode Operation No Load 2A Step Response Step Response
V V OUT OUT VOUT 50mV/DIV 50mV/DIV 50mV/DIV IOUT IOUT 500mA/DIV IOUT 1A/DIV 1A/DIV VIN = 12V 5µs/DIV 3434 G15 VIN = 12V 500µs/DIV 3434 G17 VIN = 12V 500µs/DIV 3434 G18 VOUT = 3.3V VOUT = 3.3V VOUT = 3.3V IQ = 100µA COUT = 100µF COUT = 100µF ILOAD(DC) = 500mA
U U U PI FU CTIO S NC (Pin 1):
No Connection. inductance on this path will create a voltage spike at switch off, adding to the V
SW (Pins 2, 5):
The SW pin is the emitter of the on-chip CE voltage across the internal NPN. power NPN switch. This pin is driven up to the input pin
BOOST (Pin 6):
The BOOST pin is used to provide a drive voltage during switch on time. Inductor current drives the voltage, higher than the input voltage, to the internal SW pin negative during switch off time. Negative voltage bipolar NPN power switch. Without this added voltage, the is clamped with the external catch diode. Maximum nega- typical switch voltage loss would be about 1.5V. The tive switch voltage allowed is –0.8V. additional BOOST voltage allows the switch to saturate and its voltage loss approximates that of a 0.1Ω FET
VIN (Pins 3, 4):
This is the collector of the on-chip power structure. NPN switch. VIN powers the internal control circuitry when a voltage on the BIAS pin is not present. High dI/dt edges
CT (Pin 7):
A capacitor on the CT pin determines the amount occur on this pin during switch turn on and off. Keep the of delay time between the PGFB pin exceeding its thresh- path short from the VIN pin through the input bypass old (VPGFB) and the PG pin set to a high impedance state. capacitor, through the catch diode back to SW. All trace When the PGFB pin rises above VPGFB, current is sourced 3434fb 6
W U TYPICAL PERFOR A CE CHARACTERISTICS 3.3V Dropout Operation 5V Dropout Operation Burst Mode Operation
4.0 6 VOUT = 3.3V VOUT = 5V 3.5 BOOST DIODE = DIODES INC B1100 BOOST DIODE = DIODES INC B1100 5 VOUT 50mV/DIV 3.0 4 2.5 LOAD CURRENT LOAD CURRENT 0.25A 2.0 0.25A 3 LOAD CURRENT LOAD CURRENT 1.5 2.5A 2.5A IOUT 2 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 500mA/DIV 1.0 1 V 0.5 IN = 12V 5ms/DIV 3434 G14 VOUT = 3.3V IQ = 100µA 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 1 2 3 4 5 6 INPUT VOLTAGE (V) INPUT VOLTAGE (V) 3434 G24 3434 G25
Burst Mode Operation No Load 2A Step Response Step Response
V V OUT OUT VOUT 50mV/DIV 50mV/DIV 50mV/DIV IOUT IOUT 500mA/DIV IOUT 1A/DIV 1A/DIV VIN = 12V 5µs/DIV 3434 G15 VIN = 12V 500µs/DIV 3434 G17 VIN = 12V 500µs/DIV 3434 G18 VOUT = 3.3V VOUT = 3.3V VOUT = 3.3V IQ = 100µA COUT = 100µF COUT = 100µF ILOAD(DC) = 500mA
U U U PI FU CTIO S NC (Pin 1):
No Connection. inductance on this path will create a voltage spike at switch off, adding to the V
SW (Pins 2, 5):
The SW pin is the emitter of the on-chip CE voltage across the internal NPN. power NPN switch. This pin is driven up to the input pin
BOOST (Pin 6):
The BOOST pin is used to provide a drive voltage during switch on time. Inductor current drives the voltage, higher than the input voltage, to the internal SW pin negative during switch off time. Negative voltage bipolar NPN power switch. Without this added voltage, the is clamped with the external catch diode. Maximum nega- typical switch voltage loss would be about 1.5V. The tive switch voltage allowed is –0.8V. additional BOOST voltage allows the switch to saturate and its voltage loss approximates that of a 0.1Ω FET
VIN (Pins 3, 4):
This is the collector of the on-chip power structure. NPN switch. VIN powers the internal control circuitry when a voltage on the BIAS pin is not present. High dI/dt edges
CT (Pin 7):
A capacitor on the CT pin determines the amount occur on this pin during switch turn on and off. Keep the of delay time between the PGFB pin exceeding its thresh- path short from the VIN pin through the input bypass old (VPGFB) and the PG pin set to a high impedance state. capacitor, through the catch diode back to SW. All trace When the PGFB pin rises above VPGFB, current is sourced 3434fb 6