Datasheet LT1976, LT1976B (Analog Devices) - 8

LT1976/LT1976B
W U TYPICAL PERFOR A CE CHARACTERISTICS LT1976 Step Response
VOUT 100mV/DIV 1A IOUT 500mA/DIV 0A VIN = 12V TIME (1ms/DIV) 1976 G18 VOUT = 3.3V COUT = 47μF IDC = 250mA
U U U PI FU CTIO S NC (Pins 1, 3, 5):
No Connection. Pins 1, 3, 5 are
CT (Pin 7):
A capacitor on the CT pin determines the amount electrically isolated from the LT1976. They may be con- of delay time between the PGFB pin exceeding its thresh- nected to PCB traces to aid in PCB layout. old (VPGFB) and the PG pin set to a high impedance state.
SW (Pin 2):
The SW pin is the emitter of the on-chip power When the PGFB pin rises above VPGFB, current is sourced NPN switch. This pin is driven up to the input pin voltage from the CT pin into the external capacitor. When the volt- during switch on time. Inductor current drives the SW pin age on the external capacitor reaches an internal clamp negative during switch off time. Negative voltage is clamped (VCT), the PG pin becomes a high impedance node. The with the external Schottky catch diode to prevent exces- resultant PG delay time is given by t = CCT • VCT/ICT. If the sive negative voltages. voltage on the PGFB pin drops below VPGFB, CCT will be discharged rapidly to 0V and PG will be active low with a
VIN (Pin 4):
This is the collector of the on-chip power NPN 200μA sink capability. If the CT pin is clamped (Power Good switch. VIN powers the internal control circuitry when a condition) during normal operation and SHDN is taken low, voltage on the BIAS pin is not present. High di/dt edges the CT pin will be discharged and a delay period will occur occur on this pin during switch turn on and off. Keep the when SHDN is returned high. See the Power Good section path short from the VIN pin through the input bypass in Applications Information for details. capacitor, through the catch diode back to SW. All trace inductance on this path will create a voltage spike at switch
GND (Pins 8, 17):
The GND pin connection acts as the off, adding to the V reference for the regulated output, so load regulation will CE voltage across the internal NPN. suffer if the “ground” end of the load is not at the same
BOOST (Pin 6):
The BOOST pin is used to provide a drive voltage as the GND pin of the IC. This condition will occur voltage, higher than the input voltage, to the internal when load current or other currents flow through metal bipolar NPN power switch. Without this added voltage, the paths between the GND pin and the load ground. Keep the typical switch voltage loss would be about 1.5V. The path between the GND pin and the load ground short and additional BOOST voltage allows the switch to saturate use a ground plane when possible. The GND pin also acts and its voltage loss approximates that of a 0.2Ω FET as a heat sink and should be soldered (along with the structure, but with much smaller die area. exposed leadframe) to the copper ground plane to reduce thermal resistance (see Applications Information). 1976bfg 8