Datasheet LT1956, LT1956-5 (Analog Devices) - 10

LT1956/LT1956-5
U U W U APPLICATIO S I FOR ATIO
Peak-to-peak output ripple voltage is the sum of a triwave ceramic capacitor. Although this reduction of ESR re- (created by peak-to-peak ripple current (ILP-P) times ESR) moves a useful zero in the overall loop response, this zero and a square wave (created by parasitic inductance (ESL) can be replaced by inserting a resistor (RC) in series with and ripple current slew rate). Capacitive reactance is the VC pin and the compensation capacitor CC. (See assumed to be small compared to ESR or ESL. Ceramic Capacitors in Applications Information.) dI
Peak Inductor Current and Fault Current
V = I( - )(ESR) + (ESL) RIPPLE LP P Σ dt To ensure that the inductor will not saturate, the peak in- where: ductor current should be calculated knowing the maximum load current. An appropriate inductor should then be cho- ESR = equivalent series resistance of the output sen. In addition, a decision should be made whether or not capacitor the inductor must withstand continuous fault conditions. ESL = equivalent series inductance of the output If maximum load current is 0.5A, for instance, a 0.5A capacitor inductor may not survive a continuous 2A overload condi- dI/dt = slew rate of inductor ripple current = VIN/L tion. Dead shorts will actually be more gentle on the inductor because the LT1956 has frequency and current Peak-to-peak ripple current (ILP-P) through the inductor limit foldback. and into the output capacitor is typically chosen to be between 20% and 40% of the maximum load current. It is Peak inductor and switch current can be significantly approximated by: higher than output current, especially with smaller induc- ( tors and lighter loads, so don’t omit this step. Powdered V )(V – V ) I OUT IN OUT LP-P = (V )(f)(L)
Table 2
IN
VENDOR/ VALUE IDC(MAX) DCR HEIGHT
Example: with V
PART NO. (
µ
H) (Amps) (Ohms) (mm)
IN = 12V, VOUT = 5V, L = 15µH, ESR = 0.080Ω and ESL = 10nH, output ripple voltage can be
Coiltronics
approximated as follows: UP1B-100 10 1.9 0.111 5.0 UP1B-220 22 1.2 0.254 5.0 ( )5(12− )5 UP2B-220 22 2.0 0.062 6.0 I = 0.389A LP-P ( ) UP2B-330 33 1.7 0.092 6.0 12 (15 •10 6 – )(500 •10 6–) = UP1B-150 15 1.5 0.175 5.0 dI Σ = 12 = 106 • 0.8
Coilcraft
dt − 15 • 10 6 D01813P-153HC 15 1.5 0.170 5.0 V −9 6 D01813P-103HC 10 1.9 0.111 5.0 RIPPLE = (0.389)(0.08) + (10 • 10 )(10 )(0 8 . ) D53316P-223 22 1.6 0.207 5.1 = 0.031+ 0.008 = mV 39 P-P D53316P-333 33 1.4 0.334 5.1 LP025060B-682 6.8 1.3 0.165 1.65 To reduce output ripple voltage further requires an in- crease in the inductor value with the trade-off being a
Sumida
physically larger inductor with the possibility of increased CDRH4D28-4R7 4.7 1.32 0.072 3.0 component height and cost. CDRH5D28-100 10 1.30 0.065 3.0 CDRH6D28-150 15 1.40 0.084 3.0
Ceramic Output Capacitor
CDRH6D28-180 18 1.32 0.095 3.0 An alternative way to further reduce output ripple voltage CDRH6D28-220 22 1.20 0.128 3.0 is to reduce the ESR of the output capacitor by using a CDRH6D38-220 22 1.30 0.096 4.0 1956f 10