LT1777 WBLOCK DIAGRA V V CC IN 4 10 R1 V R SHDN B SENSE 3 BIAS VBG – dV/dt SWDR ICOMP LIMITER SYNC Q2 12 OSC LOGIC SWON Q1 SGND 7 VSW 6 VC 14 I I 1 FEEDBACK FB AMP 13 VD g ±dI/dt m I I2 5 LIMITER VBG 1777 BD WWOUTPUT STAGE SI PLIFIED SCHE ATIC VIN C1 Q2 Q3 R1 Q4 R2 Q6 Q1 VSW LSENSE LMAIN SWITCH ON I1 V I SIGNAL OUT R3 + Q5 R4 VD NOTE: R3 = R4 1777 SS 7