Datasheet AD8352 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | 2 GHz Ultralow Distortion Differential RF/IF Amplifier |
| 页数 / 页 | 19 / 10 — AD8352. Data Sheet. 0.6. 1.5. tRISE (10/90) = 215ps. tFALL (10/90) = … |
| 修订版 | C |
| 文件格式/大小 | PDF / 464 Kb |
| 文件语言 | 英语 |
AD8352. Data Sheet. 0.6. 1.5. tRISE (10/90) = 215ps. tFALL (10/90) = 210ps. 0.5. –20. 1.0. 0.4. –40. ( AY. rees). E (V). 0.3. –60. Deg. HAS P. –0.5. 0.2. –80
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AD8352 Data Sheet 0.6 0 1.5 tRISE (10/90) = 215ps tFALL (10/90) = 210ps 0.5 –20 1.0 s) 0.5 n 0.4 –40 ( AY rees) E (V) L G 0.3 –60 Deg A 0 DE ( T E L UP VO RO HAS P –0.5 G 0.2 –80 0.1 –100 –1.0 0 –120 –1.5 0 100 200 300 400 500 600 700 800 900 1000 0 0.5 1.0 1.5 2.0 2.5 3.0
042 046
FREQUENCY (MHz) TIME (nsec)
05728- 05728- Figure 16. Group Delay and Phase vs. Frequency, AV = 10 dB, RL = 200 Ω Figure 19. Large Signal Output Transient Response, RL = 200 Ω, AV = 10 dB
3500 0 5 4 3000 –0.05 3 ) ) F 2500 –0.10 p (Ω ( 2 ) % 1 2000 –0.15 ANCE T G ( SISTANCE 0 ACI 1500 –0.20 RE TTLIN E –1 UT CAP S UT 1000 –0.25 INP –2 INP –3 500 –0.30 –4
052
0 –0.35 –5 0 100 200 300 400 500 600 700 800 900 1000
05728-
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
047
FREQUENCY (MHz) TIME (nsec)
05728- Figure 17. S11 Equivalent RC Parallel Network, RG = 115 Ω Figure 20. 1% Settling Time for a 2 V p-p Step Response, AV = 10 dB, RL = 200 Ω
160 0.7 6 25 z) 140 0.6 H 5 V/ ) ) 120 0.5 F p I (n 20 ( T E (Ω ) C 4 dB 100 0.4 N Y R T ( ANCE TA E T SI R 80 0.3 EN 3 15 ESIS ACI FIGU T R E CAP ISE D 60 0.2 U O OIS TP UT N 2 P L N OU A 40 0.1 UT R 10 O T 1 20 0 SPEC
053
0 –1.0 0 5 0 100 200 300 400 500 600 700 800 900 1000
054 05728-
0 50 100 150 200 250 300 350 400 FREQUENCY (MHz) GAIN SETTING RESISTOR (Ω)
05728- Figure 18. S22 Equivalent RC Parallel Network, R Figure 21. Spectral Noise Density RTI and Noise Figure vs. R G = 115 Ω G, RL = 200 Ω Rev. C | Page 10 of 19 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS NOISE DISTORTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION GAIN AND DISTORTION ADJUSTMENT (DIFFERENTIAL INPUT) SINGLE-ENDED INPUT OPERATION NARROW-BAND, THIRD-ORDER INTERMODULATION CANCELLATION HIGH PERFORMANCE ADC DRIVING LAYOUT AND TRANSMISSION LINE EFFECTS EVALUATION BOARD EVALUATION BOARD LOADING SCHEMES SOLDERING INFORMATION EVALUATION BOARD SCHEMATICS OUTLINE DIMENSIONS ORDERING GUIDE
042 046
FREQUENCY (MHz) TIME (nsec)
05728- 05728- Figure 16. Group Delay and Phase vs. Frequency, AV = 10 dB, RL = 200 Ω Figure 19. Large Signal Output Transient Response, RL = 200 Ω, AV = 10 dB
3500 0 5 4 3000 –0.05 3 ) ) F 2500 –0.10 p (Ω ( 2 ) % 1 2000 –0.15 ANCE T G ( SISTANCE 0 ACI 1500 –0.20 RE TTLIN E –1 UT CAP S UT 1000 –0.25 INP –2 INP –3 500 –0.30 –4
052
0 –0.35 –5 0 100 200 300 400 500 600 700 800 900 1000
05728-
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
047
FREQUENCY (MHz) TIME (nsec)
05728- Figure 17. S11 Equivalent RC Parallel Network, RG = 115 Ω Figure 20. 1% Settling Time for a 2 V p-p Step Response, AV = 10 dB, RL = 200 Ω
160 0.7 6 25 z) 140 0.6 H 5 V/ ) ) 120 0.5 F p I (n 20 ( T E (Ω ) C 4 dB 100 0.4 N Y R T ( ANCE TA E T SI R 80 0.3 EN 3 15 ESIS ACI FIGU T R E CAP ISE D 60 0.2 U O OIS TP UT N 2 P L N OU A 40 0.1 UT R 10 O T 1 20 0 SPEC
053
0 –1.0 0 5 0 100 200 300 400 500 600 700 800 900 1000
054 05728-
0 50 100 150 200 250 300 350 400 FREQUENCY (MHz) GAIN SETTING RESISTOR (Ω)
05728- Figure 18. S22 Equivalent RC Parallel Network, R Figure 21. Spectral Noise Density RTI and Noise Figure vs. R G = 115 Ω G, RL = 200 Ω Rev. C | Page 10 of 19 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS NOISE DISTORTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION GAIN AND DISTORTION ADJUSTMENT (DIFFERENTIAL INPUT) SINGLE-ENDED INPUT OPERATION NARROW-BAND, THIRD-ORDER INTERMODULATION CANCELLATION HIGH PERFORMANCE ADC DRIVING LAYOUT AND TRANSMISSION LINE EFFECTS EVALUATION BOARD EVALUATION BOARD LOADING SCHEMES SOLDERING INFORMATION EVALUATION BOARD SCHEMATICS OUTLINE DIMENSIONS ORDERING GUIDE