Datasheet LTC2053, LTC2053-SYNC (Analog Devices) - 10

LTC2053/LTC2053-SYNC
block DiagraM
8 V+ ZERO-DRIFT +IN 3 + OP AMP C OUT H –IN CS 7 2 – REF RG V– EN/CLK* 5 6 4 1 2053 BD *NOTE: PIN 1 IS EN ON THE LTC2053 AND CLK ON THE LTC2053-SYNC
applicaTions inForMaTion Theory of Operation ±5 Volt Operation
The LTC2053 uses an internal capacitor (CS) to sample When using the LTC2053 with supplies over 5.5V, care a differential input signal riding on a DC common mode must be taken to limit the maximum difference between voltage (see the Block Diagram). This capacitor’s charge is any of the input pins (+IN or –IN) and the REF pin to 5.5V; transferred to a second internal hold capacitor (CH) trans- if not, the device will be damaged. For example, if rail-to-rail lating the common mode of the input differential signal to input operation is desired when the supplies are at ±5V, that of the REF pin. The resulting signal is amplified by a the REF pin should be 0V, ±0.5V. As a second example, zero-drift op amp in the noninverting configuration. The if V+ is 10V and V– and REF are at 0V, the inputs should RG pin is the negative input of this op amp and allows not exceed 5.5V. external programmability of the DC gain. Simple filtering can be realized by using an external capacitor across the
Settling Time
feedback resistor. The sampling rate is 3kHz and the input sampling period during which C
Input Voltage Range
S is charged to the input differential voltage VIN is approximately 150µs. First assume that on each The input common mode voltage range of the LTC2053 input sampling period, CS is charged fully to VIN. Since is rail-to-rail. However, the following equation limits the CS = CH (= 1000pF), a change in the input will settle to size of the differential input voltage: N bits of accuracy at the op amp noninverting input after V– ≤ (V N clock cycles or 333µs(N). The settling time at the OUT +IN – V–IN) + VREF ≤ V+ – 1.3 pin is also affected by the settling of the internal op amp. Where V+IN and V–IN are the voltages of the +IN and –IN Since the gain bandwidth of the internal op amp is typically pins, respectively, VREF is the voltage at the REF pin and 200kHz, the settling time is dominated by the switched V+ is the positive supply voltage. capacitor front end for gains below 100 (see the Typical For example, with a 3V single supply and a 0V to 100mV Performance Characteristics section). differential input voltage, VREF must be between 0V and 1.6V. 2053syncfd 10 For more information www.linear.com/LTC2053 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts