Datasheet LT6556 (Analog Devices) - 8

LT6556
U U W U APPLICATIO S I FOR ATIO Power Supplies
The enable/disable times of the LT6556 are fast when The LT6556 is optimized for ±5V supplies but can be op- driven with a logic input. Turn on (from 50% ⎯E⎯N input to erated on as little as ±2.25V or a single 4.5V supply and 50% output) typically occurs in less than 50ns. Turn off as much as ±6V or a single 12V supply. Internally, each is slower, but is typically below 500ns. supply is independent to improve channel isolation.
Do not leave any supply pins disconnected or the part may Channel Select not function correctly!
The SEL pin uses the same internal threshold as the ⎯E⎯N pin and is also referenced to DGND. When the pin is logic
Enable/Shutdown
low, the channel A inputs are passed to the output. When The LT6556 has a shutdown mode controlled by the ⎯E⎯N the pin is logic high, the channel B inputs are passed to pin and referenced to the DGND pin. If the amplifi er will be the output. The pin should not be fl oated but can be tied enabled at all times, the ⎯E⎯N pin can be connected directly to DGND to force the outputs to always be channel A or to DGND. If the enable function is desired, either driving to V+ (when less than 8V) to force the outputs to always the pin above 2V or allowing the internal 46k pull-up be channel B. resistor to pull the ⎯E⎯N pin to the top rail will disable the
Truth Table
amplifi er. When disabled, the output will become very
SEL
⎯
A/B
⎯
E
⎯
N OUT
high impedance. Supply current into the amplifi er in the disabled state will be: 0 0 IN A 1 0 IN B X 1 OFF V+ V V+ – – V– I EN S = + k 46 k 80
Input Considerations
It is important that the following constraints on the DGND, The LT6556 uses input clamps referenced to the VREF pin ⎯E⎯N and SEL pins are always followed: to prevent damage to the input stage on the unselected
V+ – V
channel. Three transistors in series limit the input voltage to
DGND ≥ 4.5V -0.5V ≤ V
within three diode drops (±) from V ⎯
E
⎯
N – VDGND ≤ 5.5V
REF. VREF is nominally
V
set to half of the sum of the supplies by the 40k resistors.
SEL – VDGND ≤ 8V
A simplifi ed schematic is shown in Figure 1. In dual supply cases where V+ is less than 4.5V, DGND should be connected to a potential below ground, such as V+ V–. Since the ⎯E⎯N and SEL pins are referenced to DGND, they may need to be pulled below ground in those cases. However, 40k in order to protect the internal enable circuitry, the ⎯E⎯N pin should not be forced more than 0.5V below DGND. In single supply applications above 5.5V, an additional IN VREF resistor may be needed from the ⎯E⎯N pin to DGND if the pin is ever allowed to fl oat. For example, on a 12V single 40k supply, a 33k resistor would protect the pin from fl oating too high while still allowing the internal pull-up resistor to disable the part. 6556 F01 V– On dual ±2.25V supplies, connecting the DGND pin to V– is
Figure 1. Simplifi ed Schematic of V
the only way of ensuring that V+ – V
REF Pin and Input Clamping
DGND ≥ 4.5V. 6556f 8