Datasheet LT6555 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 650MHz Gain of 2 Triple 2:1Video Multiplexer |
| 页数 / 页 | 16 / 7 — PI FU CTIO S (GN24 Package). IN1A (Pin 1):. V– (Pin 15):. DGND (Pin 2):. … |
| 文件格式/大小 | PDF / 374 Kb |
| 文件语言 | 英语 |
PI FU CTIO S (GN24 Package). IN1A (Pin 1):. V– (Pin 15):. DGND (Pin 2):. OUT3 (Pin 16):. IN2A (Pin 3):. V+ (Pin 17):. VREF (Pin 4):
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文件文字版本
LT6555
U U U PI FU CTIO S (GN24 Package) IN1A (Pin 1):
Channel 1 Input A. This pin has a nominal
V– (Pin 15):
Negative Supply Voltage for Channel 3 Output impedance of 400kΩ and does not have any internal Stage. V– pins are not internally connected to each other termination resistor. and must all be connected externally. Proper supply bypass- ing is necessary for best performance. See the Applications
DGND (Pin 2):
Digital Ground Reference for Enable Pin. Information section. This pin is normally connected to ground.
OUT3 (Pin 16):
Channel 3 Output. It is twice the selected
IN2A (Pin 3):
Channel 2 Input A. This pin has a nominal channel 3 input and performs optimally with a 150Ω load impedance of 400kΩ and does not have any internal (a double terminated 75Ω cable). termination resistor.
V+ (Pin 17):
Positive Supply Voltage for Channels 2 and 3
VREF (Pin 4):
Voltage Reference for Input Clamping. This Output Stages. V+ pins are not internally connected to each is the tap to an internal voltage divider that defines mid- other and must all be connected externally. Proper supply supply. It is normally connected to ground in dual supply, bypassing is necessary for best performance. See the DC coupled applications. Applications Information section.
IN3A (Pin 5):
Channel 3 Input A. This pin has a nominal
OUT2 (Pin 18):
Channel 2 Output. It is twice the selected impedance of 400kΩ and does not have any internal channel 2 input and performs optimally with a 150Ω load termination resistor. (a double terminated 75Ω cable).
AGND1 (Pin 6):
Analog Ground for the 360Ω Gain Resis-
V– (Pin 19):
Negative Supply Voltage for Channels 1 and tor of Channel 1. 2 Output Stages. V– pins are not internally connected to each
IN1B (Pin 7):
Channel 1 Input B. This pin has a nominal other and must all be connected externally. Proper supply impedance of 400kΩ and does not have any internal bypassing is necessary for best performance. See the Ap- termination resistor. plications Information section.
AGND2 (Pin 8):
Analog Ground for the 360Ω Gain Resis-
OUT1 (Pin 20):
Channel 1 Output. It is twice the selected tor of Channel 2. channel 1 input and performs optimally with a 150Ω load
IN2B (Pin 9):
Channel 2 Input B. This pin has a nominal (a double terminated 75Ω cable). impedance of 400kΩ and does not have any internal
V+ (Pin 21):
Positive Supply Voltage for Channel 1 Output termination resistor. Stage. V+ pins are not internally connected to each other
AGND3 (Pin 10):
Analog Ground for the 360Ω Gain and must all be connected externally. Proper supply Resistor of Channel 3. bypassing is necessary for best performance. See the Applications Information section.
IN3B (Pin 11):
Channel 3 Input B. This pin has a nominal impedance of 400kΩ and does not have any internal
SEL (Pin 22):
Select Pin. This high impedance pin selects termination resistor. which set of inputs are sent to the output pins. When the pin is pulled low, the A inputs are selected. When the pin
V– (Pin 12):
Negative Supply Voltage. V– pins are not in- is pulled high, the B inputs are selected. ternally connected to each other and must all be connected externally. Proper supply bypassing is necessary for best
EN (Pin 23):
Enable Control Pin. An internal pull-up performance. See the Applications Information section. resistor of 46k defines the pin’s impedance and will turn the part off if the pin is unconnected. When the pin is pulled
V+ (Pins 13, 14, 24):
Positive Supply Voltage. V+ pins are low, the amplifiers are enabled. not internally connected to each other and must all be connected externally. Proper supply bypassing is neces-
Exposed Pad (Pin 25, QFN Only):
The Exposed Pad is V– sary for best performance. See the Applications Informa- and must be soldered to the PCB. It is internally connected tion section. to the QFN Pin 4, V–. 6555f 7
U U U PI FU CTIO S (GN24 Package) IN1A (Pin 1):
Channel 1 Input A. This pin has a nominal
V– (Pin 15):
Negative Supply Voltage for Channel 3 Output impedance of 400kΩ and does not have any internal Stage. V– pins are not internally connected to each other termination resistor. and must all be connected externally. Proper supply bypass- ing is necessary for best performance. See the Applications
DGND (Pin 2):
Digital Ground Reference for Enable Pin. Information section. This pin is normally connected to ground.
OUT3 (Pin 16):
Channel 3 Output. It is twice the selected
IN2A (Pin 3):
Channel 2 Input A. This pin has a nominal channel 3 input and performs optimally with a 150Ω load impedance of 400kΩ and does not have any internal (a double terminated 75Ω cable). termination resistor.
V+ (Pin 17):
Positive Supply Voltage for Channels 2 and 3
VREF (Pin 4):
Voltage Reference for Input Clamping. This Output Stages. V+ pins are not internally connected to each is the tap to an internal voltage divider that defines mid- other and must all be connected externally. Proper supply supply. It is normally connected to ground in dual supply, bypassing is necessary for best performance. See the DC coupled applications. Applications Information section.
IN3A (Pin 5):
Channel 3 Input A. This pin has a nominal
OUT2 (Pin 18):
Channel 2 Output. It is twice the selected impedance of 400kΩ and does not have any internal channel 2 input and performs optimally with a 150Ω load termination resistor. (a double terminated 75Ω cable).
AGND1 (Pin 6):
Analog Ground for the 360Ω Gain Resis-
V– (Pin 19):
Negative Supply Voltage for Channels 1 and tor of Channel 1. 2 Output Stages. V– pins are not internally connected to each
IN1B (Pin 7):
Channel 1 Input B. This pin has a nominal other and must all be connected externally. Proper supply impedance of 400kΩ and does not have any internal bypassing is necessary for best performance. See the Ap- termination resistor. plications Information section.
AGND2 (Pin 8):
Analog Ground for the 360Ω Gain Resis-
OUT1 (Pin 20):
Channel 1 Output. It is twice the selected tor of Channel 2. channel 1 input and performs optimally with a 150Ω load
IN2B (Pin 9):
Channel 2 Input B. This pin has a nominal (a double terminated 75Ω cable). impedance of 400kΩ and does not have any internal
V+ (Pin 21):
Positive Supply Voltage for Channel 1 Output termination resistor. Stage. V+ pins are not internally connected to each other
AGND3 (Pin 10):
Analog Ground for the 360Ω Gain and must all be connected externally. Proper supply Resistor of Channel 3. bypassing is necessary for best performance. See the Applications Information section.
IN3B (Pin 11):
Channel 3 Input B. This pin has a nominal impedance of 400kΩ and does not have any internal
SEL (Pin 22):
Select Pin. This high impedance pin selects termination resistor. which set of inputs are sent to the output pins. When the pin is pulled low, the A inputs are selected. When the pin
V– (Pin 12):
Negative Supply Voltage. V– pins are not in- is pulled high, the B inputs are selected. ternally connected to each other and must all be connected externally. Proper supply bypassing is necessary for best
EN (Pin 23):
Enable Control Pin. An internal pull-up performance. See the Applications Information section. resistor of 46k defines the pin’s impedance and will turn the part off if the pin is unconnected. When the pin is pulled
V+ (Pins 13, 14, 24):
Positive Supply Voltage. V+ pins are low, the amplifiers are enabled. not internally connected to each other and must all be connected externally. Proper supply bypassing is neces-
Exposed Pad (Pin 25, QFN Only):
The Exposed Pad is V– sary for best performance. See the Applications Informa- and must be soldered to the PCB. It is internally connected tion section. to the QFN Pin 4, V–. 6555f 7