Datasheet LT6555 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | 650MHz Gain of 2 Triple 2:1Video Multiplexer |
| 页数 / 页 | 16 / 9 — APPLICATIO S I FOR ATIO. Figure 1. Simplified Schematic of VREF Pin and … |
| 文件格式/大小 | PDF / 374 Kb |
| 文件语言 | 英语 |
APPLICATIO S I FOR ATIO. Figure 1. Simplified Schematic of VREF Pin and Input Clamping. Layout and Grounding
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LT6555
U U W U APPLICATIO S I FOR ATIO
V+ 40k IN VREF 40k 6555 F01 V–
Figure 1. Simplified Schematic of VREF Pin and Input Clamping
VREF voltage to the desired level. The only way to cover the Series termination resistors should be placed as close to full common mode voltage range of V– + 1V to V+ – 1V is the output pins as possible to minimize output capaci- to shift VREF up or down. Note that on a single supply, the tance. See the Typical Performance Characteristics sec- unclamped input range limits the output low swing to 2V tion for a plot of frequency response with various output (1V multiplied by the internal gain of 2). capacitors—only 10pF of parasitic output capacitance before the series termination resistor causes 6dB of The VREF pin can also be directly driven with a DC source. peaking in the frequency response! Bypassing the VREF pin is not necessary. Low ESL/ESR bypass capacitors should be placed as The inputs can be driven beyond the point at which the close to the positive and negative supply pins as possible. output clips so long as input currents are limited to less One 4700pF ceramic capacitor is recommended for both than ±10mA. Continuing to drive the input beyond the V+ and V– supply busses. Additional 470pF ceramic ca- output limit can result in increased current drive and pacitors with minimal trace length on each supply pin will slightly increased swing, but will also increase supply further improve AC and transient response as well as current and may result in delays in transient response at channel isolation. For high current drive and large-signal larger levels of overdrive. transient applications, additional 1µF to 10µF tantalums
Layout and Grounding
should be added on each supply. The smallest value capacitors should be placed closest to the package. It is imperative that care is taken in PCB layout in order to benefit from the very high speed and very low crosstalk of If the AGND pins are not connected to ground, they must the LT6555. Separate power and ground planes are highly be carefully bypassed to maintain minimal impedance recommended and trace lengths should be kept as short over frequency. Although crosstalk will vary depending as possible. If input or output traces must be run over a upon board layout, a recommended starting point for distance of several centimeters, they should use a con- bypass capacitors would be 470pF as close as possible to trolled impedance with matching series and shunt resis- each AGND pin with a single 4700pF capacitor in parallel. tances (nominally 75Ω) to maintain signal fidelity. 6555f 9
U U W U APPLICATIO S I FOR ATIO
V+ 40k IN VREF 40k 6555 F01 V–
Figure 1. Simplified Schematic of VREF Pin and Input Clamping
VREF voltage to the desired level. The only way to cover the Series termination resistors should be placed as close to full common mode voltage range of V– + 1V to V+ – 1V is the output pins as possible to minimize output capaci- to shift VREF up or down. Note that on a single supply, the tance. See the Typical Performance Characteristics sec- unclamped input range limits the output low swing to 2V tion for a plot of frequency response with various output (1V multiplied by the internal gain of 2). capacitors—only 10pF of parasitic output capacitance before the series termination resistor causes 6dB of The VREF pin can also be directly driven with a DC source. peaking in the frequency response! Bypassing the VREF pin is not necessary. Low ESL/ESR bypass capacitors should be placed as The inputs can be driven beyond the point at which the close to the positive and negative supply pins as possible. output clips so long as input currents are limited to less One 4700pF ceramic capacitor is recommended for both than ±10mA. Continuing to drive the input beyond the V+ and V– supply busses. Additional 470pF ceramic ca- output limit can result in increased current drive and pacitors with minimal trace length on each supply pin will slightly increased swing, but will also increase supply further improve AC and transient response as well as current and may result in delays in transient response at channel isolation. For high current drive and large-signal larger levels of overdrive. transient applications, additional 1µF to 10µF tantalums
Layout and Grounding
should be added on each supply. The smallest value capacitors should be placed closest to the package. It is imperative that care is taken in PCB layout in order to benefit from the very high speed and very low crosstalk of If the AGND pins are not connected to ground, they must the LT6555. Separate power and ground planes are highly be carefully bypassed to maintain minimal impedance recommended and trace lengths should be kept as short over frequency. Although crosstalk will vary depending as possible. If input or output traces must be run over a upon board layout, a recommended starting point for distance of several centimeters, they should use a con- bypass capacitors would be 470pF as close as possible to trolled impedance with matching series and shunt resis- each AGND pin with a single 4700pF capacitor in parallel. tances (nominally 75Ω) to maintain signal fidelity. 6555f 9