Datasheet LT1794 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | Dual 500mA, 200MHz xDSL Line Driver Amplifier |
| 页数 / 页 | 20 / 9 — APPLICATIO S I FOR ATIO. Logic Controlled Operating Current. Shutdown and … |
| 文件格式/大小 | PDF / 287 Kb |
| 文件语言 | 英语 |
APPLICATIO S I FOR ATIO. Logic Controlled Operating Current. Shutdown and Recovery. Figure 5. Shutdown and Recovery Timing
该数据表的模型线
文件文字版本
LT1794
U U W U APPLICATIO S I FOR ATIO Logic Controlled Operating Current Shutdown and Recovery
The DSP controller in a typical xDSL application can have The ultimate power saving action on a completely idle port I/O pins assigned to provide logic control of the LT1794 is to fully shut down the line driver by pulling the SHDN pin line driver operating current. As shown in Figure 4 one or to within 0.4V of the SHDNREF potential. As shown in two logic control inputs can control two or four different Figure 5 complete shutdown occurs in less than 10µs and, operating modes. The logic inputs add or subtract current more importantly, complete recovery from the shut down to the SHDN input to set the operating current. The one state to full operation occurs in less than 2µs. The biasing logic input example selects the supply current to be either circuitry in the LT1794 reacts very quickly to bring the full power, 10mA per amplifier or just 2mA per amplifier, amplifiers back to normal operation. which significantly reduces the driver power consumption while maintaining less than 2Ω output impedance to frequencies less than 1MHz. This low power mode retains termination impedance at the amplifier outputs and the VSHDN line driving back termination resistors. With this termina- SHDNREF = 0V tion, while a DSL port is not transmitting data, it can still sense a received signal from the line across the back- termination resistors and respond accordingly. AMPLIFIER OUTPUT The two logic input control provides two intermediate (approximately 7mA per amplifier and 5mA per amplifier) operating levels between full power and termination modes. 1794 F05 These modes can be useful for overall system power management when full power transmissions are not
Figure 5. Shutdown and Recovery Timing
necessary.
Two Control Inputs
12V OR VLOGIC
RESISTOR VALUES (k
Ω
)
R
R
V SHDN
SHDN TO VCC (12V) RSHDN TO VLOGIC
LOGIC RC1
VLOGIC 3V 3.3V 5V 3V 3.3V 5V
VC1 SHDN
RSHDN
40.2 43.2 60.4 4.99 6.81 19.6 R 0V C0 V 2k
R
C0
C1
11.5 13.0 21.5 8.66 10.7 20.5
RCO
19.1 22.1 36.5 14.3 17.8 34.0
V V C1 C0 SUPPLY CURRENT PER AMPLIFIER (mA) H H
10 10 10 10 10 10
H L
7 7 7 7 7 7 SHDNREF
L H
5 5 5 5 5 5
L L
2 2 2 2 2 2
One Control Input
12V OR VLOGIC
RESISTOR VALUES (k
Ω
) R
R
SHDN TO VCC (12V) RSHDN TO VLOGIC
V SHDN LOGIC RC
VLOGIC 3V 3.3V 5V 3V 3.3V 5V
0V VC SHDN
RSHDN
40.2 43.2 60.4 4.99 6.81 19.6
R
2k
C
7.32 8.25 13.7 5.49 6.65 12.7
VC SUPPLY CURRENT PER AMPLIFIER (mA) H
10 10 10 10 10 10
L
2 2 2 2 2 2 1794 F04 SHDNREF
Figure 4. Providing Logic Input Control of Operating Current
9
U U W U APPLICATIO S I FOR ATIO Logic Controlled Operating Current Shutdown and Recovery
The DSP controller in a typical xDSL application can have The ultimate power saving action on a completely idle port I/O pins assigned to provide logic control of the LT1794 is to fully shut down the line driver by pulling the SHDN pin line driver operating current. As shown in Figure 4 one or to within 0.4V of the SHDNREF potential. As shown in two logic control inputs can control two or four different Figure 5 complete shutdown occurs in less than 10µs and, operating modes. The logic inputs add or subtract current more importantly, complete recovery from the shut down to the SHDN input to set the operating current. The one state to full operation occurs in less than 2µs. The biasing logic input example selects the supply current to be either circuitry in the LT1794 reacts very quickly to bring the full power, 10mA per amplifier or just 2mA per amplifier, amplifiers back to normal operation. which significantly reduces the driver power consumption while maintaining less than 2Ω output impedance to frequencies less than 1MHz. This low power mode retains termination impedance at the amplifier outputs and the VSHDN line driving back termination resistors. With this termina- SHDNREF = 0V tion, while a DSL port is not transmitting data, it can still sense a received signal from the line across the back- termination resistors and respond accordingly. AMPLIFIER OUTPUT The two logic input control provides two intermediate (approximately 7mA per amplifier and 5mA per amplifier) operating levels between full power and termination modes. 1794 F05 These modes can be useful for overall system power management when full power transmissions are not
Figure 5. Shutdown and Recovery Timing
necessary.
Two Control Inputs
12V OR VLOGIC
RESISTOR VALUES (k
Ω
)
R
R
V SHDN
SHDN TO VCC (12V) RSHDN TO VLOGIC
LOGIC RC1
VLOGIC 3V 3.3V 5V 3V 3.3V 5V
VC1 SHDN
RSHDN
40.2 43.2 60.4 4.99 6.81 19.6 R 0V C0 V 2k
R
C0
C1
11.5 13.0 21.5 8.66 10.7 20.5
RCO
19.1 22.1 36.5 14.3 17.8 34.0
V V C1 C0 SUPPLY CURRENT PER AMPLIFIER (mA) H H
10 10 10 10 10 10
H L
7 7 7 7 7 7 SHDNREF
L H
5 5 5 5 5 5
L L
2 2 2 2 2 2
One Control Input
12V OR VLOGIC
RESISTOR VALUES (k
Ω
) R
R
SHDN TO VCC (12V) RSHDN TO VLOGIC
V SHDN LOGIC RC
VLOGIC 3V 3.3V 5V 3V 3.3V 5V
0V VC SHDN
RSHDN
40.2 43.2 60.4 4.99 6.81 19.6
R
2k
C
7.32 8.25 13.7 5.49 6.65 12.7
VC SUPPLY CURRENT PER AMPLIFIER (mA) H
10 10 10 10 10 10
L
2 2 2 2 2 2 1794 F04 SHDNREF
Figure 4. Providing Logic Input Control of Operating Current
9