LT6558 APPLICATIONS INFORMATIONProgrammable Input Bias no-signal amplifi er input bias condition according to the following relationship: The LT6558 contains circuitry that provides a user-pro- grammed bias voltage to the inputs of all three amplifi er V • . k V PIN sections. The internal biasing feature is designed to mini- BIAS I ( N) = 16 9 1 R mize external component count in AC-coupled applica- SET tions, but may be defeated if external biasing is desired. where VPIN16 = 0.044V typical. Figure 1 shows the simplifi ed equivalent circuit feeding For single 5V supply operation, a 158Ω programming the noninverting input of each amplifi er. A programming resistor is generally optimal. In applications that demand resistor from Pin 16 to GND (Pin 2) establishes the nominal maximum amplifi er linearity, or if external biasing is V+ preferred (in DC-coupled applications, for example), the internal biasing circuitry may be disabled by leaving Pin V 16 open. With BCV (Pin 16) open, input loading is ap- I = PIN16 RSET proximately 450kΩ. 2.5k Shutdown Control IN 9.1k The LT6558 may be placed into a shutdown mode, where all three amplifi er sections are deactivated and power sup- 6558 F01 ply draw is reduced to approximately 10µA. When the EN pin is left open, an internal 40k pull-up resistor brings the Figure 1. Simplifi ed Programmable Input Bias Circuit Diagram pin to V+ and the part enters the shutdown mode. Pulling the pin more than approximately 1.5V below V+ will en- V+ able the LT6558 (see Figure 2 for equivalent circuit). The pull-down current required to activate the part is typically 125µA. In most applications, the EN pin is simply con- 40k nected to ground (for continuous operation) or driven directly by a CMOS-level logic gate (see Figure 3 for examples). Response time is typically 50ns for enabling, BIAS and 1µs for shutdown. In shutdown mode, the feedback CIRCUITRY resistors remain connected between the output pins and EN 6558 F02 the individual ground (or V– connected) pins. Figure 2. Simplifi ed Shutdown Circuit Diagram V+ V+ 1 EN 1 LT6558 LT6558 DISABLE EN DISABLE 2 2 6558 F03 (3a) Open Drain or Open Collector(3b) CMOS Gate with Shared SupplyFigure 3. Suitable Shutdown Pin Drive Circuits 6558f 9