Datasheet LT1818, LT1819 (Analog Devices) - 11
| 制造商 | Analog Devices |
| 描述 | 400MHz, 2500V/μs, 9mA Single Operational Amplifiers |
| 页数 / 页 | 18 / 11 — APPLICATIONS INFORMATION. Slew Rate. Circuit Operation. Power Dissipation |
| 文件格式/大小 | PDF / 1.2 Mb |
| 文件语言 | 英语 |
APPLICATIONS INFORMATION. Slew Rate. Circuit Operation. Power Dissipation
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LT1818/LT1819
APPLICATIONS INFORMATION Slew Rate
Example: LT1819IS8 at 85°C, VS = ±5V, RL = 100Ω The slew rate of the LT1818/LT1819 is proportional to the PDMAX = (10V) • (14mA) + (2.5V)2/100Ω = 202.5mW differential input voltage. Highest slew rates are therefore T seen in the lowest gain confi gurations. For example, a 6V JMAX = 85°C + (2 • 202.5mW) • (150°C/W) = 146°C output step with a gain of 10 has a 0.6V input step, whereas
Circuit Operation
at unity gain there is a 6V input step. The LT1818/LT1819 is tested for slew rate at a gain of –1. Lower slew rates The LT1818/LT1819 circuit topology is a true voltage occur in higher gain confi gurations, whereas the highest feedback amplifi er that has the slewing behavior of a cur- slew rate (2500V/μs) occurs in a noninverting unity-gain rent feedback amplifi er. The operation of the circuit can confi guration. be understood by referring to the Simplifi ed Schematic. Complementary NPN and PNP emitter followers buffer
Power Dissipation
the inputs and drive an internal resistor. The input voltage appears across the resistor, generating a current that is The LT1818/LT1819 combine high speed and large output mirrored into the high impedance node. drive in small packages. It is possible to exceed the maxi- mum junction temperature specifi cation (150°C) under Complementary followers form an output stage that buf- certain conditions. Maximum junction temperature (T fer the gain node from the load. The input resistor, input J) is calculated from the ambient temperature (T stage transconductance and the capacitor on the high A), power dissipation per amplifi er (P impedance node determine the bandwidth. The slew rate D) and number of amplifi ers (n) as follows: is determined by the current available to charge the gain node capacitance. This current is the differential input TJ = TA + (n • PD • θJA) voltage divided by R1, so the slew rate is proportional to Power dissipation is composed of two parts. The fi rst is the input step. Highest slew rates are therefore seen in due to the quiescent supply current and the second is the lowest gain confi gurations. due to on-chip dissipation caused by the load current. The worst-case load-induced power occurs when the output voltage is at 1/2 of either supply voltage (or the maximum swing if less than 1/2 the supply voltage). Therefore PDMAX is: PDMAX = (V+ – V–) • (ISMAX) + (V+/2)2/RL or PDMAX = (V+ – V–) • (ISMAX) + (V+ – VOMAX) • (VOMAX/RL) 18189fb 11 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION E LECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION TYPICAL APPLICATION SIMPLIFIED SCHEMATIC PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS
APPLICATIONS INFORMATION Slew Rate
Example: LT1819IS8 at 85°C, VS = ±5V, RL = 100Ω The slew rate of the LT1818/LT1819 is proportional to the PDMAX = (10V) • (14mA) + (2.5V)2/100Ω = 202.5mW differential input voltage. Highest slew rates are therefore T seen in the lowest gain confi gurations. For example, a 6V JMAX = 85°C + (2 • 202.5mW) • (150°C/W) = 146°C output step with a gain of 10 has a 0.6V input step, whereas
Circuit Operation
at unity gain there is a 6V input step. The LT1818/LT1819 is tested for slew rate at a gain of –1. Lower slew rates The LT1818/LT1819 circuit topology is a true voltage occur in higher gain confi gurations, whereas the highest feedback amplifi er that has the slewing behavior of a cur- slew rate (2500V/μs) occurs in a noninverting unity-gain rent feedback amplifi er. The operation of the circuit can confi guration. be understood by referring to the Simplifi ed Schematic. Complementary NPN and PNP emitter followers buffer
Power Dissipation
the inputs and drive an internal resistor. The input voltage appears across the resistor, generating a current that is The LT1818/LT1819 combine high speed and large output mirrored into the high impedance node. drive in small packages. It is possible to exceed the maxi- mum junction temperature specifi cation (150°C) under Complementary followers form an output stage that buf- certain conditions. Maximum junction temperature (T fer the gain node from the load. The input resistor, input J) is calculated from the ambient temperature (T stage transconductance and the capacitor on the high A), power dissipation per amplifi er (P impedance node determine the bandwidth. The slew rate D) and number of amplifi ers (n) as follows: is determined by the current available to charge the gain node capacitance. This current is the differential input TJ = TA + (n • PD • θJA) voltage divided by R1, so the slew rate is proportional to Power dissipation is composed of two parts. The fi rst is the input step. Highest slew rates are therefore seen in due to the quiescent supply current and the second is the lowest gain confi gurations. due to on-chip dissipation caused by the load current. The worst-case load-induced power occurs when the output voltage is at 1/2 of either supply voltage (or the maximum swing if less than 1/2 the supply voltage). Therefore PDMAX is: PDMAX = (V+ – V–) • (ISMAX) + (V+/2)2/RL or PDMAX = (V+ – V–) • (ISMAX) + (V+ – VOMAX) • (VOMAX/RL) 18189fb 11 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION E LECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION TYPICAL APPLICATION SIMPLIFIED SCHEMATIC PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS