Datasheet LT1636 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | Over-The-Top Micropower Rail-to-Rail Input and Output Op Amp |
| 页数 / 页 | 16 / 10 — TYPICAL PERFOR A CE CHARACTERISTICS. Open-Loop Gain. Large-Signal … |
| 文件格式/大小 | PDF / 403 Kb |
| 文件语言 | 英语 |
TYPICAL PERFOR A CE CHARACTERISTICS. Open-Loop Gain. Large-Signal Response. Small-Signal Response. APPLICATIONS INFORMATION
该数据表的模型线
文件文字版本
LT1636
W U TYPICAL PERFOR A CE CHARACTERISTICS Open-Loop Gain Large-Signal Response Small-Signal Response
B A A: RL = 2k µV/DIV) B C B: RL = 10k C C: RL = 50k (100 A CHANGE IN INPUT OFFSET VOLTAGE 1636 G24 V –10V 0V 10V 1636 G25 1636 G26 S = ±15V V V OUTPUT VOLTAGE (5V/DIV) S = ±15V S = ±15V AV = –1 AV = 1
U U W U APPLICATIONS INFORMATION Supply Voltage
cause the voltage at which operation switches from the PNP stage to the NPN stage to move towards V+. The input The positive supply pin of the LT1636 should be bypassed offset voltage of the NPN stage is untrimmed and is with a small capacitor (about 0.01µF) within an inch of the typically 600µV. pin. When driving heavy loads an additional 4.7µF electro- lytic capacitor should be used. When using split supplies, A Schottky diode in the collector of each NPN transistor of the same is true for the negative supply pin. the NPN input stage allows the LT1636 to operate with either or both of its inputs above V+. At about 0.3V above The LT1636 is protected against reverse battery voltages V+ the NPN input transistor is fully saturated and the input up to 27V. In the event a reverse battery condition occurs, bias current is typically 3µA at room temperature. The the supply current is less than 1nA. input offset voltage is typically 600µV when operating When operating the LT1636 on total supplies of 20V or above V+. The LT1636 will operate with its input 44V above more, the supply must not be brought up faster than 1µs. V– regardless of V+. This is especially true if low ESR bypass capacitors are The inputs are protected against excursions as much as used. A series RLC circuit is formed from the supply lead 22V below V – by an internal 1k resistor in series with each inductance and the bypass capacitor. 5Ω of resistance in input and a diode from the input to the negative supply. the supply or the bypass capacitor will dampen the tuned There is no output phase reversal for inputs up to 5V below circuit enough to limit the rise time. V –. There are no clamping diodes between the inputs and the maximum differential input voltage is 44V.
Inputs
The LT1636 has two input stages, NPN and PNP (see
Output
Simplified Schematic), resulting in three distinct operat- The output voltage swing of the LT1636 is affected by in- ing regions as shown in the Input Bias Current vs Common put overdrive as shown in the typical performance curves. Mode typical performance curve. When monitoring voltages within 100mV of V+, gain For input voltages about 0.8V or more below V+, the PNP should be taken to keep the output from clipping. input stage is active and the input bias current is typically The output of the LT1636 can be pulled up to 27V beyond – 4nA. When the input voltage is about 0.5V or less from V+ with less than 1nA of leakage current, provided that V+ V+, the NPN input stage is operating and the input bias is less than 0.5V. current is typically 10nA. Increases in temperature will 1636fc 10
W U TYPICAL PERFOR A CE CHARACTERISTICS Open-Loop Gain Large-Signal Response Small-Signal Response
B A A: RL = 2k µV/DIV) B C B: RL = 10k C C: RL = 50k (100 A CHANGE IN INPUT OFFSET VOLTAGE 1636 G24 V –10V 0V 10V 1636 G25 1636 G26 S = ±15V V V OUTPUT VOLTAGE (5V/DIV) S = ±15V S = ±15V AV = –1 AV = 1
U U W U APPLICATIONS INFORMATION Supply Voltage
cause the voltage at which operation switches from the PNP stage to the NPN stage to move towards V+. The input The positive supply pin of the LT1636 should be bypassed offset voltage of the NPN stage is untrimmed and is with a small capacitor (about 0.01µF) within an inch of the typically 600µV. pin. When driving heavy loads an additional 4.7µF electro- lytic capacitor should be used. When using split supplies, A Schottky diode in the collector of each NPN transistor of the same is true for the negative supply pin. the NPN input stage allows the LT1636 to operate with either or both of its inputs above V+. At about 0.3V above The LT1636 is protected against reverse battery voltages V+ the NPN input transistor is fully saturated and the input up to 27V. In the event a reverse battery condition occurs, bias current is typically 3µA at room temperature. The the supply current is less than 1nA. input offset voltage is typically 600µV when operating When operating the LT1636 on total supplies of 20V or above V+. The LT1636 will operate with its input 44V above more, the supply must not be brought up faster than 1µs. V– regardless of V+. This is especially true if low ESR bypass capacitors are The inputs are protected against excursions as much as used. A series RLC circuit is formed from the supply lead 22V below V – by an internal 1k resistor in series with each inductance and the bypass capacitor. 5Ω of resistance in input and a diode from the input to the negative supply. the supply or the bypass capacitor will dampen the tuned There is no output phase reversal for inputs up to 5V below circuit enough to limit the rise time. V –. There are no clamping diodes between the inputs and the maximum differential input voltage is 44V.
Inputs
The LT1636 has two input stages, NPN and PNP (see
Output
Simplified Schematic), resulting in three distinct operat- The output voltage swing of the LT1636 is affected by in- ing regions as shown in the Input Bias Current vs Common put overdrive as shown in the typical performance curves. Mode typical performance curve. When monitoring voltages within 100mV of V+, gain For input voltages about 0.8V or more below V+, the PNP should be taken to keep the output from clipping. input stage is active and the input bias current is typically The output of the LT1636 can be pulled up to 27V beyond – 4nA. When the input voltage is about 0.5V or less from V+ with less than 1nA of leakage current, provided that V+ V+, the NPN input stage is operating and the input bias is less than 0.5V. current is typically 10nA. Increases in temperature will 1636fc 10