Datasheet ADP5003 (Analog Devices) - 3

Data Sheet ADP5003 SPECIFICATIONS
VPVIN1 = VPVINSYS = 4.2 V to 15 V, VPVIN2 = 0.65 V to 5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
INPUT VOLTAGE RANGE VPVIN1, VPVINSYS 4.2 15 V VPVIN2 0.65 5 V THERMAL SHUTDOWN Threshold TSD 155 °C TJ rising Hysteresis TSD-HYS 15 °C SYNC INPUT Input Logic High VIH 1.1 V Low VIL 0.4 V Input Leakage Current VI-LEAKAGE 1 µA ADAPTIVE MODE INPUT (VSET1) Input Rising Threshold VADPR 2.5 V Input Hysteresis VADPH 16 mV PRECISION ENABLING High Level Threshold VTH_H 1.125 1.15 1.175 V Low Level Threshold VTH_L 1.025 1.05 1.075 V Shutdown Mode VTH_S 0.4 V EN1, EN2 Pull-Down Resistance RENPD 1.5 MΩ INPUT CURRENT Both Channels Enabled ISTBY-NOSW 0.5 1 mA No load Both Channels Disabled ISHUTDOWN 5 10 µA TJ = −40°C to +125°C REFOUT CHARACTERISTICS Output Voltage VREFOUT 2.0 V Accuracy −0.5 +0.5 % VREG AND VREG_LDO CHARACTERISTICS Output Voltage VREG, VREG_LDO 5 V Accuracy −2 +2 % Current Limit1 10 mA POWER-GOOD PIN (PWRGD) Lower Limit PWRGDF 80 85 90 % Nominal VOUT1 and nominal VFB2P/VFB2N low threshold Lower Hysteresis PWRGDFH 2.5 % Nominal VOUT1 and nominal VFB2P/VFB2N low hysteresis Output Voltage Level VOL 25 50 mV Sink current (ISINK) = 1 mA Deglitch Time tPWRGDD 60 µs PVINSYS UNDERVOLTAGE LOCKOUT (UVLO) Input Voltage Rising UVLOPVINSYSRISE 4.2 V Falling UVLOPVINSYSFALL 3.9 V 1 Do not use VREG and VREG_LDO to supply the external loads. This current limit protects against a pin short to ground. Rev. 0 | Page 3 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS LDO SPECIFICATIONS ADAPTIVE HEADROOM CONTROLLER SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER MANAGEMENT UNIT Adaptive Headroom Control Precision Enable/Shutdown Undervoltage Lockout (UVLO) Thermal Shutdown (TSD) Active Pull Down Soft Start (SS) Power-Good BUCK REGULATOR Control Scheme Oscillator Frequency Control External Oscillator Synchronization Buck Startup Current-Limit and Short-Circuit Protection LDO REGULATOR LDO Startup Current Limit Differential Remote Sensing POWER-GOOD OUTPUT VOLTAGE OF THE BUCK REGULATOR OUTPUT VOLTAGE OF THE LDO REGULATOR VOLTAGE CONVERSION LIMITATIONS COMPONENT SELECTION Output Capacitors Input Capacitor Inductor COMPENSATION COMPONENTS DESIGN JUNCTION TEMPERATURE BUCK REGULATOR DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY FOR THE BUCK REGULATOR SETTING THE OUTPUT VOLTAGE FOR THE BUCK REGULATOR SELECTING THE INDUCTOR FOR THE BUCK REGULATOR SELECTING THE OUTPUT CAPACITOR FOR THE BUCK REGULATOR DESIGNING THE COMPENSATION NETWORK FOR THE BUCK REGULATOR SELECTING THE INPUT CAPACITOR FOR THE BUCK REGULATOR ADAPTIVE HEADROOM CONTROL DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY FOR THE BUCK REGULATOR USING ADAPTIVE HEADROOM CONTROL SETTING THE OUTPUT VOLTAGE FOR THE BUCK REGULATOR USING ADAPTIVE HEADROOM CONTROL SELECTING THE INDUCTOR FOR THE BUCK REGULATOR USING ADAPTIVE HEADROOM CONTROL SELECTING THE OUTPUT CAPACITORS FOR THE BUCK REGULATOR USING ADAPTIVE HEADROOM CONTROL SELECTING THE INPUT CAPACITOR FOR THE BUCK REGULATOR USING ADAPTIVE HEADROOM CONTROL RECOMMENDED BUCK EXTERNAL COMPONENTS FOR THE BUCK REGULATOR BUCK CONFIGURATIONS INDEPENDENT ADAPTIVE HEADROOM LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE