Datasheet LTC7124 (Analog Devices) - 9

制造商Analog Devices
描述17V, Dual 3.5A Synchronous Step-Down Regulator with Ultralow Quiescent Current
页数 / 页22 / 9 — OPERATION. Main Control Loop. Forced Continuous Mode Operation. “Power …
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OPERATION. Main Control Loop. Forced Continuous Mode Operation. “Power Good” Status Output. Low Current Operation

OPERATION Main Control Loop Forced Continuous Mode Operation “Power Good” Status Output Low Current Operation

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LTC7124
OPERATION
The LTC7124 is a dual-channel, synchronous step-down When the load increases and pulls the output out of sleep, regulator featuring a constant frequency, peak current the part resumes switching in its active state. mode architecture. It is capable of providing up to 3.5A of To optimize efficiency, Burst Mode can be enabled by tying output current across a wide VIN range for each channel, the MODE/SYNC pin to INTV while regulating with ultralow quiescent current when no CC. In Burst Mode, the minimum peak current level is set to be 800mA, thereby overriding load is present. Each channel is enabled by raising its any I respective RUN pin voltage above 1V. TH voltage that commands a lower peak current. To minimize VOUT ripple, pulse skipping mode can be
Main Control Loop
enabled by grounding the MODE/SYNC pin. In this case, In normal operation, the top power switch (N-channel the minimum peak current level is set to be 200mA, lower MOSFET) is turned on at the onset of a clock cycle. Once than in Burst Mode. As a result, compared to Burst Mode, the inductor current has ramped up to a certain peak value, pulse skipping mode produces a lower output voltage as determined by the I ripple, but at a slightly lower efficiency at light loads. TH voltage, the top power switch turns off, and the bottom switch (N-channel MOSFET) turns If a channel is programmed to operate at half peak current on for the remainder of the clock cycle. This ITH voltage with the ILIM pin, the minimum peak current levels likewise is the output of the error amplifier, which compares the scale accordingly by half to 400mA in Burst Mode and FB voltage to an internal 0.6V reference. When the load 100mA in pulse skipping mode. increases, the FB voltage falls below the reference value, thereby causing the ITH voltage to increase until the
Forced Continuous Mode Operation
average inductor current matches the new load current. If operating in DCM is undesirable, the LTC7124 can be Due to a wide range of possible operating frequencies, the put in forced continuous mode by tying the MODE/SYNC error amplifier can be internally or externally compensated pin between 1V and INTV based on the I CC –1.2V. In forced continuous TH pin. mode, the part will switch every clock cycle regardless of The frequency of operation is programmed by the value of the value of the output load current. the RT resistor. If a clock signal is applied to the MODE/SYNC pin, an internal phase-locked loop will synchronize the R
“Power Good” Status Output
T programmed frequency to the external clock. If the RT The PGOOD pin output indicates whether the output volt- pin is tied to INTVCC, spread spectrum operation around age is within ±7.5% of the regulation point. Immediately 2.25MHz (±12%) is enabled, and external clock syncing after the output voltage enters this ±7.5% window, the is not allowed. PGOOD output becomes high impedance. Conversely, when the output voltage falls out of regulation, the PGOOD
Low Current Operation
open-drain output is pulled low after a 32 clock cycle delay. At light load current levels, the LTC7124 can automatically transition from continuous operation to one of two dis-
High Duty Cycle/Dropout Operation
continuous conduction modes (DCMs) of operation, if As the operating duty cycle of a channel approaches programmed to do so. In both these modes, Burst Mode 100%, the part enters dropout operation for that channel. and pulse skipping, as long as the ITH voltage is lower than In this very high duty cycle condition, if the bottom power the zero current level, the switcher will halt switching and switch has been off for 32 clock cycles, the regulator will operate in an ultralow quiescent current sleep state. In this automatically turn off the top power switch and turn on sleep state, the part will draw only 5.5μA of quiescent cur- the bottom power switch for the last 25% of the next clock rent from VIN1 if only one channel is enabled and 8μA of cycle to charge the BOOST-SW capacitor. quiescent current from VIN1 if both channels are enabled. 7124fa For more information www.linear.com/LTC7124 9