Datasheet LTC3623 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | 15V, ±5A Rail-to-Rail Synchronous Buck Regulator |
| 页数 / 页 | 30 / 8 — pin FuncTions ISET (Pin 1):. PGND (Pins 9, 10, 11, 12, Exposed Pad Pin … |
| 文件格式/大小 | PDF / 1.5 Mb |
| 文件语言 | 英语 |
pin FuncTions ISET (Pin 1):. PGND (Pins 9, 10, 11, 12, Exposed Pad Pin 25):. OUT (Pin 13):. PGOOD (Pin 2):. IN (Pin 17):
该数据表的模型线
文件文字版本
LTC3623
pin FuncTions ISET (Pin 1):
Accurate 50µA Current Source. Positive
PGND (Pins 9, 10, 11, 12, Exposed Pad Pin 25):
input to the error amplifier. Connect an external resistor Power Ground. Return path of Internal Power MOSFETs. from this pin to signal GND to program the VOUT voltage. Connect these pins to the negative terminals of the input Connecting an external capacitor from ISET to ground and output capacitors. The exposed pad must be soldered will soft start the output voltage and reduce current to the PCB ground for electrical contact and rated thermal inrush at the input cap when turning on. VOUT can also performance. be programmed by driving ISET directly with an accurate
V
external voltage supply from 0 to V
OUT (Pin 13):
Output Voltage Pin. Negative input of the IN, in which case the error amplifier which is driven to be the same voltage as external supply would be sinking this 50µA. Do not drive ISET. ISET above VIN or below GND.
SV PGOOD (Pin 2):
Output Power Good with Open-Drain
IN (Pin 17):
Signal VIN. Input voltage to power internal bias circuitry. SV Logic. PGOOD is pulled to ground when the PGFB pin IN must be above 4V. is more than 0.63V or less than 0.54V. If PGFB is tied
BOOST (Pin 18):
Boosted Floating Driver Supply for to INTVCC, the open drain logic on PGOOD is disabled. Internal Top Power MOSFET. The (+) terminal of the boot- PGOOD voltage is referred to GSNS. strap capacitor connects here. This pin swings from a diode voltage drop below INTV
RUN (Pin 3):
Run Control Input. Enables chip operation by CC up to PVIN + INTVCC. tying RUN above 1.45V. Tying RUN below 1V shuts down
INTVCC (Pin 19):
Internal 5V Regulator Output. The inter- switching regulator. Tying RUN below 0.4V shuts off the nal power drivers and control circuits are powered from entire chip. RUN voltage is referred to GSNS. this voltage. Decouple this pin to PGND with a minimum of 1µF low ESR ceramic capacitor.
GSNS (Pin 4):
System Ground SENSE. Ground reference for the RUN, PGOOD and MODE/SYNC pins. For positive
PGFB (Pin 20):
Power Good Feedback. Place a resistor VOUT applications, connect GSNS to PGND. For negative divider on VOUT to detect power good level. If PGFB is VOUT applications, connect GSNS to ground return of the more than 0.63V or less than 0.54V, PGOOD will be pulled system board. down. Tie PGFB to INTVCC to disable PGOOD function. Tying PGFB to a voltage between 0.67V and 4V will force
PVIN (Pins 5, 16):
Power VIN. Input voltage connected continuous synchronous operation regardless of the to the drain of the top power NMOS. Must be decoupled MODE/SYNC state. to PGND with capacitor close to PVIN pin. PVIN operates down to 1.5V as long as SVIN > 4V.
IMON (Pin 21):
Current Monitor Pin. There will be a cur- rent equal to 21µA • I
SW (Pins 6, 15):
Switch Node Connection to External OUT coming out of the IMON pin. Place a resistor in parallel with a filtering capacitor (10nF) Inductor. Voltage swing of SW is from a diode voltage from IMON to GND to report I drop below ground to PV OUT. When the voltage on IN. IMON is above 2.35V, IOUT will be limited. IMON can also
MODE/SYNC (Pin 8):
Operation Mode Select. Tie this pin be used to program VOUT to compensate for output volt- to INTVCC to force continuous synchronous operation at age drop at the load due to wire resistance by injecting the all output loads. Tying it to GSNS enables discontinuous IMON current into a portion of the ISET resistor. mode operation at light loads. Applying an external clock
VIN_REG (Pin 22):
Control Pin for V signal to this pin will synchronize switching frequency IN regulation. Tie this pin to INTV to the external clock. MODE/SYNC voltage is referred to CC for buck converter operation where VOUT is regulated to ISET. Tie this pin to a resistor divider from V GSNS. During external clock synchronization, R IN T value to GND to enable input voltage regulation. When VIN_REG should be set up such that the free running frequency is drops below 1.45V, the system will reduce the inductor within ±30% of the external clock frequency. current to keep VIN from dropping. 3623fa 8 For more information www.linear.com/LTC3623
pin FuncTions ISET (Pin 1):
Accurate 50µA Current Source. Positive
PGND (Pins 9, 10, 11, 12, Exposed Pad Pin 25):
input to the error amplifier. Connect an external resistor Power Ground. Return path of Internal Power MOSFETs. from this pin to signal GND to program the VOUT voltage. Connect these pins to the negative terminals of the input Connecting an external capacitor from ISET to ground and output capacitors. The exposed pad must be soldered will soft start the output voltage and reduce current to the PCB ground for electrical contact and rated thermal inrush at the input cap when turning on. VOUT can also performance. be programmed by driving ISET directly with an accurate
V
external voltage supply from 0 to V
OUT (Pin 13):
Output Voltage Pin. Negative input of the IN, in which case the error amplifier which is driven to be the same voltage as external supply would be sinking this 50µA. Do not drive ISET. ISET above VIN or below GND.
SV PGOOD (Pin 2):
Output Power Good with Open-Drain
IN (Pin 17):
Signal VIN. Input voltage to power internal bias circuitry. SV Logic. PGOOD is pulled to ground when the PGFB pin IN must be above 4V. is more than 0.63V or less than 0.54V. If PGFB is tied
BOOST (Pin 18):
Boosted Floating Driver Supply for to INTVCC, the open drain logic on PGOOD is disabled. Internal Top Power MOSFET. The (+) terminal of the boot- PGOOD voltage is referred to GSNS. strap capacitor connects here. This pin swings from a diode voltage drop below INTV
RUN (Pin 3):
Run Control Input. Enables chip operation by CC up to PVIN + INTVCC. tying RUN above 1.45V. Tying RUN below 1V shuts down
INTVCC (Pin 19):
Internal 5V Regulator Output. The inter- switching regulator. Tying RUN below 0.4V shuts off the nal power drivers and control circuits are powered from entire chip. RUN voltage is referred to GSNS. this voltage. Decouple this pin to PGND with a minimum of 1µF low ESR ceramic capacitor.
GSNS (Pin 4):
System Ground SENSE. Ground reference for the RUN, PGOOD and MODE/SYNC pins. For positive
PGFB (Pin 20):
Power Good Feedback. Place a resistor VOUT applications, connect GSNS to PGND. For negative divider on VOUT to detect power good level. If PGFB is VOUT applications, connect GSNS to ground return of the more than 0.63V or less than 0.54V, PGOOD will be pulled system board. down. Tie PGFB to INTVCC to disable PGOOD function. Tying PGFB to a voltage between 0.67V and 4V will force
PVIN (Pins 5, 16):
Power VIN. Input voltage connected continuous synchronous operation regardless of the to the drain of the top power NMOS. Must be decoupled MODE/SYNC state. to PGND with capacitor close to PVIN pin. PVIN operates down to 1.5V as long as SVIN > 4V.
IMON (Pin 21):
Current Monitor Pin. There will be a cur- rent equal to 21µA • I
SW (Pins 6, 15):
Switch Node Connection to External OUT coming out of the IMON pin. Place a resistor in parallel with a filtering capacitor (10nF) Inductor. Voltage swing of SW is from a diode voltage from IMON to GND to report I drop below ground to PV OUT. When the voltage on IN. IMON is above 2.35V, IOUT will be limited. IMON can also
MODE/SYNC (Pin 8):
Operation Mode Select. Tie this pin be used to program VOUT to compensate for output volt- to INTVCC to force continuous synchronous operation at age drop at the load due to wire resistance by injecting the all output loads. Tying it to GSNS enables discontinuous IMON current into a portion of the ISET resistor. mode operation at light loads. Applying an external clock
VIN_REG (Pin 22):
Control Pin for V signal to this pin will synchronize switching frequency IN regulation. Tie this pin to INTV to the external clock. MODE/SYNC voltage is referred to CC for buck converter operation where VOUT is regulated to ISET. Tie this pin to a resistor divider from V GSNS. During external clock synchronization, R IN T value to GND to enable input voltage regulation. When VIN_REG should be set up such that the free running frequency is drops below 1.45V, the system will reduce the inductor within ±30% of the external clock frequency. current to keep VIN from dropping. 3623fa 8 For more information www.linear.com/LTC3623