Datasheet ADP5054 (Analog Devices)

Quad Buck Regulator Integrated Power Solution Data Sheet ADP5054 FEATURES TYPICAL APPLICATION CIRCUIT Wide input voltage range: 4.5 V to 15.5 V ADP5054 ±1.5% output accuracy over full temperature range VREG INTERNAL SYNC/MODE C1 VDD 250 kHz to 2 MHz adjustable switching frequency with VREG OSCILLATOR 100mA RT C0 individual ½× frequency option FB1 PVIN1 Power regulation 4.5V TO 15.5V BST1 SW1 Channel 1 and Channel 2 C2 C3 L1 CHANNEL 1 VOUT1 COMP1 BUCK (2A/4A/6A) VREG Programmable 2 A/4 A/6 A sync buck regulators with Q1 C4 EN1 DL1 low-side FET drivers 1 VREG IM CFG12 PGND IL Channel 3 and Channel 4: 2.5 A sync buck regulators (SS, 1/2 × f 2 SW, IM PARALLEL) DL2 IL Flexible parallel operation SW2 Q2 C5 L2 Single 12 A output (Channel 1 and Channel 2 in parallel) PVIN2 CHANNEL 2 VOUT2 VREG BUCK COMP2 (2A/4A/6A) C6 C7 Single 5 A output (Channel 3 and Channel 4 in parallel) BST2 EN2 FB2 Low 1/f noise density IVE T PWRGD EC 40 μV rms at 0.8 V L REF for 10 Hz to 100 kHz E BST3 PVIN3 S SW3 Precision enable with 0.811 V accurate threshold C8 C9 L3 VOUT3 COMP3 CHANNEL 3 BUCK Active output discharge switch FB3 EN3 (2.5A) C10 PGND3 FPWM/PSM mode selection VREG CFG34 Frequency synchronization input or output (SS, 1/2 × f BST4 SW, PARALLEL, SW4 Power-good flag for Channel 1 output SCLKSET) C12 L4 VOUT4 PVIN4 CHANNEL 4 BUCK UVLO, OCP, and TSD protection FB4 C11 COMP4 (2.5A) C13 PGND4 48-lead, 7 mm × 7 mm LFCSP EN4 −40°C to +125°C operational junctional temperature range
1 0 -0
EXPOSED PAD
17 126
APPLICATIONS
Figure 1.
FPGA and processor applications Small cell base stations Security and surveillance Medical applications GENERAL DESCRIPTION
The ADP5054 combines four high performance buck regulators in or synchronized to an external clock from 250 kHz to 2 MHz, a 48-lead LFCSP package that meets demanding performance and and an individual ½× frequency configuration is available for board space requirements. The device enables direct connection each channel. to high input voltages of up to 15.5 V with no preregulators. The ADP5054 contains an individual precision enable pin on each Channel 1 and Channel 2 integrate high-side power MOSFETs and channel for easy power-up sequencing. The internal low 1/f noise low-side MOSFET drivers. External NFETs can be used in low-side reference is implemented in the ADP5054 for noise sensitive power devices to achieve an efficiency optimized solution and applications. to deliver a programmable output current of 2 A, 4 A, or 6 A.
Table 1. Related Products
Combining Channel 1 and Channel 2 in a parallel configuration
Model Channels I2C Package
provides a single output with up to 12 A of current. ADP5050 Four bucks, one LDO Yes 48-Lead LFCSP Channel 3 and Channel 4 integrate both high-side and low-side ADP5051 Four bucks, supervisory Yes 48-Lead LFCSP MOSFETs to deliver an output current of 2.5 A. Combining ADP5052 Four bucks, one LDO No 48-Lead LFCSP Channel 3 and Channel 4 in a parallel configuration can ADP5053 Four bucks, supervisory No 48-Lead LFCSP provide a single output with up to 5 A of current. ADP5054 Four high current bucks No 48-Lead LFCSP The switching frequency of the ADP5054 can be programmed
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Document Outline Features Applications Typical Application Circuit General Description Revision History Detailed Functional Block Diagram Specifications Buck Regulator Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Buck Regulator Operational Modes PWM Mode PSM Mode Forced PWM and Automatic PWM/PSM Modes Adjustable and Fixed Output Voltage Internal Regulators (VREG and VDD) Separate Supply Applications Low-Side Device Selection Bootstrap Circuitry Active Output Discharge Switch Precision Enabling Oscillator Phase Shift Synchronization Input/Output Soft Start Parallel Operation Startup with Precharged Output Current-Limit Protection Frequency Foldback Pulse Skip in Maximum Duty Short-Circuit Protection (SCP) Latch-Off Protection Short-Circuit Latch-Off Mode Undervoltage Lockout (UVLO) Power-Good Function Thermal Shutdown Applications Information ADIsimPower Design Tool Programming the Output Voltage Voltage Conversion Limitations Current-Limit Setting Soft Start Setting Inductor Selection Output Capacitor Selection Input Capacitor Selection Low-Side Power Device Selection Programming the UVLO Input Compensation Components Design Power Dissipation Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown Junction Temperature Design Examples Setting the Switching Frequency Setting the Output Voltage Setting the Current Limit Selecting the Inductor Selecting the Output Capacitor Selecting the Low-Side MOSFET Designing the Compensation Network Selecting the Soft Start Time Selecting the Input Capacitor Printed Circuit Board Layout Recommendations Typical Application Circuit Factory Default Options Outline Dimensions Ordering Guide