Datasheet ADP5080 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | High Efficiency Integrated Power Solution for Multicell Lithium Ion Applications |
| 页数 / 页 | 64 / 1 — High Efficiency Integrated Power Solution. for Multicell Lithium Ion … |
| 修订版 | A |
| 文件格式/大小 | PDF / 1.5 Mb |
| 文件语言 | 英语 |
High Efficiency Integrated Power Solution. for Multicell Lithium Ion Applications. Data Sheet. ADP5080. FEATURES
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High Efficiency Integrated Power Solution for Multicell Lithium Ion Applications Data Sheet ADP5080 FEATURES FUNCTIONAL BLOCK DIAGRAM Wide input voltage range: 4.0 V to 15 V SCL High efficiency architecture I2C INTERFACE OSCILLATOR SDA Up to 2 MHz switching frequency 6 synchronous rectification dc-to-dc converters VOLTAGE ENABLE CONTROL REFERENCE Channel 1 buck regulator: 3 A maximum LOGIC FAULT Channel 2 buck regulator: 1.15 A maximum CHARGE PUMP Channel 3 buck regulator: 1.5 A maximum Channel 4 buck regulator: 0.8 A maximum 4V TO 15V LDO1 5.0V TO 5.5V, 400mA Channel 5 buck regulator: 2 A maximum LDO2 3V TO 3.3V, 300mA Channel 6 configurable buck or buck boost regulator CH1 BUCK 2 A maximum for buck regulator configuration 4V TO 15V REGULATOR 0.80V TO 1.20V, 3A 1.5 A maximum for buck boost regulator configuration CH2 BUCK 4V TO 15V 1.0V TO 3.3V, 1.15A REGULATOR Channel 7 high voltage, high performance LDO regulator: CH 3 BUCK 30 mA maximum 4V TO 15V 1.2V TO 1.8V/ADJ, 1.5A REGULATOR 2 low quiescent current keep-alive LDO regulators CH 4 BUCK 4V TO 15V 1.8V TO 3.55V/ADJ, 0.8A REGULATOR LDO1 regulator: 400 mA maximum CH 5 BUCK LDO2 regulator: 300 mA maximum 4V TO 15V 3.0V TO 5.0V, 2A REGULATOR Control circuit CH 6 BUCK BOOST 3.5V TO 5.5V/ADJ 4V TO 15V Charge pump for internal switching driver power supply REGULATOR BUCK ONLY: 2A BUCK BOOST: 1.5A I2C-programmable output levels and power sequencing CH7 LDO 5V TO 25V 5V TO 12V, 30mA REGULATOR Package: 72-ball, 4.5 mm × 4.0 mm × 0.6 mm WLCSP
001
(0.5 mm pitch)
11639- Figure 1.
APPLICATIONS DSLR cameras Non-reflex (mirrorless) cameras Portable instrumentation GENERAL DESCRIPTION
The ADP5080 is a fully integrated, high efficiency power All these features help to minimize the number of external solution for multicell lithium ion battery applications. The components and PCB space required, providing significant device can connect directly to the battery, which eliminates advantages for portable applications. The switching frequency the need for preregulators and, therefore, increases the battery is selectable on each channel from 750 kHz to 2 MHz. life of the system. Key functions for power applications, such as soft start, selectable The ADP5080 integrates two keep-alive LDO regulators, five preset output voltage, and flexible power-up and power-down synchronous buck regulators, a configurable four-switch buck sequences, are provided on chip and are programmable via the boost regulator, and a high voltage LDO regulator. The ADP5080 I2C interface with fused factory defaults. The ADP5080 is available is a highly integrated power solution that incorporates all power in a 72-ball WLCSP 0.5 mm pitch package. MOSFETs, feedback loop compensation, voltage setting resistor dividers, and discharge switches, as well as a charge pump to generate a global bootstrap voltage.
Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Housekeeping Block Specifications DC-to-DC Converter Block Specifications Linear Regulator Block Specifications I2C Interface Timing Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Application Circuit Theory of Operation UVLO and POR Undervoltage Lockout (UVLO) Power-On Reset (POR) Discharge Switch Keep-Alive LDO Linear Regulators LDO1 VISW1 Input Current Limit for LDO1 Discharge Switch for LDO1 LDO2 VISW2 Input Current Limit for LDO2 Discharge Switch for LDO2 DC-to-DC Converter Channels Channel 1, Channel 2, and Channel 3: Buck Regulators with Flex-Mode Architecture Selecting the Output Voltage, Channel 1 to Channel 3 Current-Limit Protection, Channel 1 to Channel 3 Discharge Switch, Channel 1 to Channel 3 Gate Scaling (Channel 1 Only) Dynamic Voltage Scaling (DVS) Function Channel 4 and Channel 5: Current Mode Buck Regulators Selecting the Output Voltage, Channel 4 and Channel 5 Current-Limit Protection, Channel 4 and Channel 5 Discharge Switch, Channel 4 and Channel 5 Channel 6: Buck or Buck Boost Regulator Buck Only Configuration Buck Boost Configuration Selecting the Output Voltage, Channel 6 Current-Limit Protection, Channel 6 Discharge Switch, Channel 6 Light Load and Other Modes of Operation for the DC-to-DC Converter Channels Slew Rate Adjustment Forced PWM (FPWM) Mode Auto DCM Auto PSM Selecting Light Load Switching Modes Switching Clock External Synchronization Mode Selecting the Internal Clock Frequency Selecting the External Resistor Phase Shifting CLKO Pin Soft Start Function Channel 7: High Voltage LDO Regulator Selecting the Output Voltage, Channel 7 Discharge Switch, Channel 7 Charge Pump Charge Pump Switching Frequency Capacitor Selection Protection Diode Using the Charge Pump as the Channel 7 Input Supply Enabling and Disabling the Output Channels Sequencer Mode Manual Mode EN Function EN34 Function Power-Good Function Fault Function Undervoltage Protection (UVP) UVP Detection Delay Channel 5 Standalone Undervoltage Detection Option Recovering from UVP Overvoltage Protection (OVP) OVP Detection Delay Recovering from OVP Applications Information Component Selection for the Buck and Buck Boost Regulators Setting the Output Voltage (Adjustable Mode Channels) Selecting the Inductor Selecting the Input Capacitor Selecting the Output Capacitor Component Selection for the LDO Regulators Selecting the Capacitors PCB Layout Recommendations Sensitive Signal Treatment Grounding External Component Placement and Signal Routing Thermal Considerations I2C Interface SDA and SCL Pins I2C Address Self-Clearing Register Bits I2C Interface Timing Diagrams Control Register Information Control Register Map CONTROL REGISTER DETAILS Register 1: DSCG (Discharge Switch Control), Address 0x01 Register 2: SFTTIM1234 (Soft Start Time for Channel 1, Channel 2, Channel 3, and Channel 4), Address 0x02 Register 3: SFTTIM567 (Soft Start Time for Channel 5, Channel 6, and Channel 7), Address 0x03 Register 4: EN_DLY12 (Enable Delay Time for Channel 1 and Channel 2), Address 0x04 Register 5: EN_DLY34 (Enable Delay Time for Channel 3 and Channel 4), Address 0x05 Register 6: EN_DLY56 (Enable Delay Time for Channel 5 and Channel 6), Address 0x06 Register 7: EN_DLY7 (Enable Delay Time for Channel 7), Address 0x07 Register 8: DIS_DLY12 (Disable Delay Time for Channel 1 and Channel 2), Address 0x08 Register 9: DIS_DLY34 (Disable Delay Time for Channel 3 and Channel 4), Address 0x09 Register 10: DIS_DLY56 (Disable Delay Time for Channel 5 and Channel 6), Address 0x0A Register 11: DIS_DLY7 (Disable Delay Time for Channel 7), Address 0x0B Register 12: VID1 (Output Voltage for Channel 1), Address 0x0C Register 13: VID23 (Output Voltage for Channel 2 and Channel 3), Address 0x0D Register 14: VID45 (Output Voltage for Channel 4 and Channel 5), Address 0x0E Register 15: VID6 (Output Voltage for Channel 6), Address 0x0F Register 16: VID7_LDO12 (Output Voltage for Channel 7, LDO1, and LDO2), Address 0x10 Register 17: DVS12 (DVS Control for Channel 1 and Channel 2), Address 0x11 Register 18: SEL_FREQ (Switching Frequency for Channel 1 to Channel 6), Address 0x12 Register 19: SEL_FREQ_CP (Charge Pump Frequency), Address 0x13 Register 20: SEL_PHASE (Switching Phase for Channel 1 to Channel 6), Address 0x14 Register 23: PROT_DLY (Undervoltage/Overvoltage Protection Delay Times), Address 0x17 Register 24: PWRG (Power-Good Status), Address 0x18 Register 25: MASK_PWRG (Power-Good Masked Channels), Address 0x19 Register 26: UVPST (Undervoltage Protection Status), Address 0x1A Register 27: OVPST (Overvoltage Protection Status), Address 0x1B Register 28: AUTO-PSM (Auto PSM or Forced PWM Mode for Channel 1 to Channel 6), Address 0x1C Register 29: SEQ_MODE (Sequencer Mode), Address 0x1D Register 30: ADJ_BST_VTH6 (Adjust Boost Kick-In Threshold and Regulation Mode for Channel 6), Address 0x1E Register 31: OPT_SR_ADJ (Slew Rate Adjustment for Channel 1 to Channel 6), Address 0x1F Register 32: DCM56_GSCAL1 (Auto DCM for Channel 5 and Channel 6, Gate Scaling for Channel 1), Address 0x20 Register 33: SEL_INP_LDO12 (Input Selection for LDO1 and LDO2), Address 0x21 Register 34: SEL_IND_UV5 (Independent UVP Control for Channel 5), Address 0x22 Register 35: OPTION_SEL (Channel 1 Output Voltage Reduction, Disable Delay Time Increase, EN34 Function), Address 0x23 Register 48: PCTRL (Channel Enable Control), Address 0x30 Factory Default Options Outline Dimensions Ordering Guide
001
(0.5 mm pitch)
11639- Figure 1.
APPLICATIONS DSLR cameras Non-reflex (mirrorless) cameras Portable instrumentation GENERAL DESCRIPTION
The ADP5080 is a fully integrated, high efficiency power All these features help to minimize the number of external solution for multicell lithium ion battery applications. The components and PCB space required, providing significant device can connect directly to the battery, which eliminates advantages for portable applications. The switching frequency the need for preregulators and, therefore, increases the battery is selectable on each channel from 750 kHz to 2 MHz. life of the system. Key functions for power applications, such as soft start, selectable The ADP5080 integrates two keep-alive LDO regulators, five preset output voltage, and flexible power-up and power-down synchronous buck regulators, a configurable four-switch buck sequences, are provided on chip and are programmable via the boost regulator, and a high voltage LDO regulator. The ADP5080 I2C interface with fused factory defaults. The ADP5080 is available is a highly integrated power solution that incorporates all power in a 72-ball WLCSP 0.5 mm pitch package. MOSFETs, feedback loop compensation, voltage setting resistor dividers, and discharge switches, as well as a charge pump to generate a global bootstrap voltage.
Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Housekeeping Block Specifications DC-to-DC Converter Block Specifications Linear Regulator Block Specifications I2C Interface Timing Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Application Circuit Theory of Operation UVLO and POR Undervoltage Lockout (UVLO) Power-On Reset (POR) Discharge Switch Keep-Alive LDO Linear Regulators LDO1 VISW1 Input Current Limit for LDO1 Discharge Switch for LDO1 LDO2 VISW2 Input Current Limit for LDO2 Discharge Switch for LDO2 DC-to-DC Converter Channels Channel 1, Channel 2, and Channel 3: Buck Regulators with Flex-Mode Architecture Selecting the Output Voltage, Channel 1 to Channel 3 Current-Limit Protection, Channel 1 to Channel 3 Discharge Switch, Channel 1 to Channel 3 Gate Scaling (Channel 1 Only) Dynamic Voltage Scaling (DVS) Function Channel 4 and Channel 5: Current Mode Buck Regulators Selecting the Output Voltage, Channel 4 and Channel 5 Current-Limit Protection, Channel 4 and Channel 5 Discharge Switch, Channel 4 and Channel 5 Channel 6: Buck or Buck Boost Regulator Buck Only Configuration Buck Boost Configuration Selecting the Output Voltage, Channel 6 Current-Limit Protection, Channel 6 Discharge Switch, Channel 6 Light Load and Other Modes of Operation for the DC-to-DC Converter Channels Slew Rate Adjustment Forced PWM (FPWM) Mode Auto DCM Auto PSM Selecting Light Load Switching Modes Switching Clock External Synchronization Mode Selecting the Internal Clock Frequency Selecting the External Resistor Phase Shifting CLKO Pin Soft Start Function Channel 7: High Voltage LDO Regulator Selecting the Output Voltage, Channel 7 Discharge Switch, Channel 7 Charge Pump Charge Pump Switching Frequency Capacitor Selection Protection Diode Using the Charge Pump as the Channel 7 Input Supply Enabling and Disabling the Output Channels Sequencer Mode Manual Mode EN Function EN34 Function Power-Good Function Fault Function Undervoltage Protection (UVP) UVP Detection Delay Channel 5 Standalone Undervoltage Detection Option Recovering from UVP Overvoltage Protection (OVP) OVP Detection Delay Recovering from OVP Applications Information Component Selection for the Buck and Buck Boost Regulators Setting the Output Voltage (Adjustable Mode Channels) Selecting the Inductor Selecting the Input Capacitor Selecting the Output Capacitor Component Selection for the LDO Regulators Selecting the Capacitors PCB Layout Recommendations Sensitive Signal Treatment Grounding External Component Placement and Signal Routing Thermal Considerations I2C Interface SDA and SCL Pins I2C Address Self-Clearing Register Bits I2C Interface Timing Diagrams Control Register Information Control Register Map CONTROL REGISTER DETAILS Register 1: DSCG (Discharge Switch Control), Address 0x01 Register 2: SFTTIM1234 (Soft Start Time for Channel 1, Channel 2, Channel 3, and Channel 4), Address 0x02 Register 3: SFTTIM567 (Soft Start Time for Channel 5, Channel 6, and Channel 7), Address 0x03 Register 4: EN_DLY12 (Enable Delay Time for Channel 1 and Channel 2), Address 0x04 Register 5: EN_DLY34 (Enable Delay Time for Channel 3 and Channel 4), Address 0x05 Register 6: EN_DLY56 (Enable Delay Time for Channel 5 and Channel 6), Address 0x06 Register 7: EN_DLY7 (Enable Delay Time for Channel 7), Address 0x07 Register 8: DIS_DLY12 (Disable Delay Time for Channel 1 and Channel 2), Address 0x08 Register 9: DIS_DLY34 (Disable Delay Time for Channel 3 and Channel 4), Address 0x09 Register 10: DIS_DLY56 (Disable Delay Time for Channel 5 and Channel 6), Address 0x0A Register 11: DIS_DLY7 (Disable Delay Time for Channel 7), Address 0x0B Register 12: VID1 (Output Voltage for Channel 1), Address 0x0C Register 13: VID23 (Output Voltage for Channel 2 and Channel 3), Address 0x0D Register 14: VID45 (Output Voltage for Channel 4 and Channel 5), Address 0x0E Register 15: VID6 (Output Voltage for Channel 6), Address 0x0F Register 16: VID7_LDO12 (Output Voltage for Channel 7, LDO1, and LDO2), Address 0x10 Register 17: DVS12 (DVS Control for Channel 1 and Channel 2), Address 0x11 Register 18: SEL_FREQ (Switching Frequency for Channel 1 to Channel 6), Address 0x12 Register 19: SEL_FREQ_CP (Charge Pump Frequency), Address 0x13 Register 20: SEL_PHASE (Switching Phase for Channel 1 to Channel 6), Address 0x14 Register 23: PROT_DLY (Undervoltage/Overvoltage Protection Delay Times), Address 0x17 Register 24: PWRG (Power-Good Status), Address 0x18 Register 25: MASK_PWRG (Power-Good Masked Channels), Address 0x19 Register 26: UVPST (Undervoltage Protection Status), Address 0x1A Register 27: OVPST (Overvoltage Protection Status), Address 0x1B Register 28: AUTO-PSM (Auto PSM or Forced PWM Mode for Channel 1 to Channel 6), Address 0x1C Register 29: SEQ_MODE (Sequencer Mode), Address 0x1D Register 30: ADJ_BST_VTH6 (Adjust Boost Kick-In Threshold and Regulation Mode for Channel 6), Address 0x1E Register 31: OPT_SR_ADJ (Slew Rate Adjustment for Channel 1 to Channel 6), Address 0x1F Register 32: DCM56_GSCAL1 (Auto DCM for Channel 5 and Channel 6, Gate Scaling for Channel 1), Address 0x20 Register 33: SEL_INP_LDO12 (Input Selection for LDO1 and LDO2), Address 0x21 Register 34: SEL_IND_UV5 (Independent UVP Control for Channel 5), Address 0x22 Register 35: OPTION_SEL (Channel 1 Output Voltage Reduction, Disable Delay Time Increase, EN34 Function), Address 0x23 Register 48: PCTRL (Channel Enable Control), Address 0x30 Factory Default Options Outline Dimensions Ordering Guide