Datasheet ADP5053 (Analog Devices)

Integrated Power Solution with Quad Buck Regulators and Supervisory Circuits Data Sheet ADP5053 FEATURES TYPICAL APPLICATION CIRCUIT Wide input voltage range: 4.5 V to 15.0 V ADP5053 SYNC/MODE VREG ±1.5% output accuracy over full temperature range INT VREG VDD OSCILLATOR C1 100mA RT 250 kHz to 1.4 MHz adjustable switching frequency C0 FB1 Adjustable/fixed output options via factory fuse PVIN1 4.5V TO 15V BST1 Power regulation SW1 C3 CHANNEL 1 L1 C2 VOUT1 COMP1 BUCK REGULATOR Channel 1 and Channel 2: programmable 1.2 A/2.5 A/4 A (1.2A/2.5A/4A) VREG C4 EN1 Q1 sync buck regulators with low-side FET driver DL1 SS12 RILIM1 Channel 3 and Channel 4: 1.2 A sync buck regulators PGND R DL2 ILIM2 Single 8 A output (Channel 1 and Channel 2 operated in parallel) Q2 PVIN2 Precision enable with 0.8 V accurate threshold C5 CHANNEL 2 VREG SW2 VOUT2 BUCK REGULATOR COMP2 L2 Active output discharge switch (1.2A/2.5A/4A) C6 C7 BST2 EN2 FPWM or automatic PWM/PSM selection FB2 PWRGD Frequency synchronization input or output PVIN3 BST3 Optional latch-off protection on OVP/OCP failure C8 C9 L3 SW3 VOUT3 COMP3 CHANNEL 3 Power-good flag on selected channels BUCK REGULATOR C10 (1.2A) FB3 EN3 UVLO, OCP, and TSD protection PGND3 SS34 Open-drain processor reset with external adjustable BST4 threshold monitoring PVIN4 C12 L4 SW4 VOUT4 CHANNEL 4 Watchdog refresh input C11 BUCK REGULATOR COMP4 FB4 C13 (1.2A) Manual reset input EN4 VREG PGND4 RSTO APPLICATIONS WDI WATCHDOG MR AND RESET VTH VOUTx Small cell base stations FPGA and processor applications
001
EXPOSED PAD
1636-
Security and surveillance
1 Figure 1.
Medical applications GENERAL DESCRIPTION
The ADP5053 combines four high performance buck regulators, a The switching frequency of the ADP5053 can be programmed supervisory circuit, a watchdog timer, and a manual reset in a or synchronized to an external clock. The ADP5053 contains a 48-lead LFCSP package that meets demanding performance and precision enable pin on each channel for easy power-up sequencing board space requirements. The device enables direct connection or adjustable UVLO threshold. to high input voltages up to 15.0 V with no preregulators. The ADP5053 contains supervisory circuits that monitor the Channel 1 and Channel 2 integrate high-side power MOSFET and voltage level. The watchdog timer can generate a reset if the low-side MOSFET drivers. External NFETs can be used in low-side WDI pin is not toggled within a preset timeout period. Processor power devices to achieve an efficiency optimized solution and reset mode or system power on/off switch mode can be selected deliver a programmable output current of 1.2 A, 2.5 A, or 4 A. for manual reset functionality. Combining Channel 1 and Channel 2 in a paral el configuration
Table 1. Family Models
can provide a single output with up to 8 A of current.
Model Channels I2C Package
Channel 3 and Channel 4 integrate both high-side and low-side ADP5050 Four bucks, one LDO Yes 48-Lead LFCSP MOSFETs to deliver an output current of 1.2 A. ADP5051 Four bucks, supervisory Yes 48-Lead LFCSP ADP5052 Four bucks, one LDO No 48-Lead LFCSP ADP5053 Four bucks, supervisory No 48-Lead LFCSP ADP5054 Four high current bucks No 48-Lead LFCSP
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Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS SUPERVISORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES Pulse-Width Modulation (PWM) Mode Power Save Mode (PSM) Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGES INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK Pulse Skip Mode Under Maximum Duty Cycle HICCUP PROTECTION LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode Overvoltage Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION THERMAL SHUTDOWN SUPERVISORY CIRCUIT Reset Output Watchdog Input Manual Reset Input Processor Manual Reset Mode Power On/Off Switch Mode APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL PROGRAMMING THE ADJUSTABLE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown JUNCTION TEMPERATURE DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR RECOMMENDED EXTERNAL COMPONENTS CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE