Datasheet ADP2386 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | 20 V, 6 A, Synchronous Step-Down DC-to-DC Regulator |
| 页数 / 页 | 24 / 5 — Data Sheet. ADP2386. ABSOLUTE MAXIMUM RATINGS Table 2. THERMAL … |
| 修订版 | C |
| 文件格式/大小 | PDF / 860 Kb |
| 文件语言 | 英语 |
Data Sheet. ADP2386. ABSOLUTE MAXIMUM RATINGS Table 2. THERMAL RESISTANCE. Parameter. Rating. Table 3. Thermal Resistance
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Data Sheet ADP2386 ABSOLUTE MAXIMUM RATINGS Table 2. THERMAL RESISTANCE Parameter Rating
θJA is specified for the worst-case conditions, that is, a device PVIN, SW, EN, PGOOD −0.3 V to +22 V soldered in a 4-layer, JEDEC standard circuit board for surface- SW 10 ns Transient −2.5 V to +22 V mount packages. SW 100 ns Transient −1 V to +22 V BST V
Table 3. Thermal Resistance
SW + 6 V FB, SS, COMP, SYNC, RT −0.3 V to +6 V
Package Type
θ
JA
θ
JC Unit
VREG −0.3 V to +12 V 24-Lead LFCSP_WQ 42.6 6.8 (EP, SW) °C/W PGND to GND −0.3 V to +0.3 V 2.3 (EP, GND) Operating Junction Temperature Range −40°C to +125°C Storage Temperature Range −65°C to +150°C
ESD CAUTION
Soldering Conditions JEDEC J-STD-020 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. C | Page 5 of 24 Document Outline Features Applications Typical Applications Circuit General Description Table of Contents Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Functional Block Diagram Theory of Operation Control Scheme Precision Enable/Shutdown Internal Regulator (VREG) Bootstrap Circuitry Oscillator Synchronization Soft Start Power Good Peak Current-Limit and Short-Circuit Protection Overvoltage Protection (OVP) Undervoltage Lockout (UVLO) Thermal Shutdown Applications Information Input Capacitor Selection Output Voltage Setting Voltage Conversion Limitations Inductor Selection Output Capacitor Selection Programming the Input Voltage UVLO Compensation Design ADIsimPower Design Tool Design Example Output Voltage Setting (Design Example) Frequency Setting Inductor Selection (Design Example) Output Capacitor Selection (Design Example) Compensation Components Soft Start Time Program Input Capacitor Selection (Design Example) Recommended External Components Circuit Board Layout Recommendations Typical Applications Circuits Outline Dimensions Ordering Guide
θJA is specified for the worst-case conditions, that is, a device PVIN, SW, EN, PGOOD −0.3 V to +22 V soldered in a 4-layer, JEDEC standard circuit board for surface- SW 10 ns Transient −2.5 V to +22 V mount packages. SW 100 ns Transient −1 V to +22 V BST V
Table 3. Thermal Resistance
SW + 6 V FB, SS, COMP, SYNC, RT −0.3 V to +6 V
Package Type
θ
JA
θ
JC Unit
VREG −0.3 V to +12 V 24-Lead LFCSP_WQ 42.6 6.8 (EP, SW) °C/W PGND to GND −0.3 V to +0.3 V 2.3 (EP, GND) Operating Junction Temperature Range −40°C to +125°C Storage Temperature Range −65°C to +150°C
ESD CAUTION
Soldering Conditions JEDEC J-STD-020 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. C | Page 5 of 24 Document Outline Features Applications Typical Applications Circuit General Description Table of Contents Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Functional Block Diagram Theory of Operation Control Scheme Precision Enable/Shutdown Internal Regulator (VREG) Bootstrap Circuitry Oscillator Synchronization Soft Start Power Good Peak Current-Limit and Short-Circuit Protection Overvoltage Protection (OVP) Undervoltage Lockout (UVLO) Thermal Shutdown Applications Information Input Capacitor Selection Output Voltage Setting Voltage Conversion Limitations Inductor Selection Output Capacitor Selection Programming the Input Voltage UVLO Compensation Design ADIsimPower Design Tool Design Example Output Voltage Setting (Design Example) Frequency Setting Inductor Selection (Design Example) Output Capacitor Selection (Design Example) Compensation Components Soft Start Time Program Input Capacitor Selection (Design Example) Recommended External Components Circuit Board Layout Recommendations Typical Applications Circuits Outline Dimensions Ordering Guide