Datasheet ADP2380 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | 20 V, 4 A synchronous Step-Down Regulator with Low-Side Driver |
| 页数 / 页 | 28 / 5 — Data Sheet. ADP2380. ABSOLUTE MAXIMUM RATINGS Table 2. Parameter. Rating. … |
| 文件格式/大小 | PDF / 946 Kb |
| 文件语言 | 英语 |
Data Sheet. ADP2380. ABSOLUTE MAXIMUM RATINGS Table 2. Parameter. Rating. THERMAL INFORMATION. Table 3. Thermal Resistance
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Data Sheet ADP2380 ABSOLUTE MAXIMUM RATINGS Table 2.
Absolute maximum ratings apply individually only, not in
Parameter Rating
combination. Unless otherwise specified, all other voltages are referenced to GND. PVIN, PGOOD −0.3 V to +22 V SW −1 V to +22 V
THERMAL INFORMATION
BST VSW + 6 V UVLO, FB, EN/SS, COMP, SYNC, RT −0.3 V to +6 V
Table 3. Thermal Resistance
VREG, LD −0.3 V to +12 V
Package Type
θ
JA Unit
PGND to GND −0.3 V to +0.3 V 16-lead TSSOP_EP 39.48 °C/W Operating Junction Temperature Range −40°C to +125°C θJA is specified for the worst-case conditions, that is, a device Storage Temperature Range −65°C to +150°C soldered in circuit board (4-layer, JEDEC standard board) for Soldering Conditions JEDEC J-STD-020 surface-mount packages. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
ESD CAUTION
rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 5 of 28 Document Outline Features Applications Typical Applications Circuit General Description Revision History Specifications Absolute Maximum Ratings Thermal Information ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Functional Block Diagram Theory of Operation Control Scheme Internal Regulator (VREG) Bootstrap Circuitry Low-Side Driver Oscillator Synchronization Enable and Soft Start Power Good Peak Current-Limit and Short-Circuit Protection Overvoltage Protection (OVP) Undervoltage Lockout (UVLO) Thermal Shutdown Applications Information Input Capacitor Selection Output Voltage Setting Voltage Conversion Limitations Inductor Selection Output Capacitor Selection Low-Side Power Device Selection Programming Input Voltage UVLO Compensation Design Compensation Network Between COMP and GND Compensation Network Between COMP and FB ADIsimPower Design Tool Design Example Output Voltage Setting Frequency Setting Inductor Selection Output Capacitor Selection Low-Side MOSFET Selection Compensation Components Soft Start Time Program Input Capacitor Selection Recommended External Components Circuit Board Layout Recommendations Typical Applications Circuits Outline Dimensions Ordering Guide
Absolute maximum ratings apply individually only, not in
Parameter Rating
combination. Unless otherwise specified, all other voltages are referenced to GND. PVIN, PGOOD −0.3 V to +22 V SW −1 V to +22 V
THERMAL INFORMATION
BST VSW + 6 V UVLO, FB, EN/SS, COMP, SYNC, RT −0.3 V to +6 V
Table 3. Thermal Resistance
VREG, LD −0.3 V to +12 V
Package Type
θ
JA Unit
PGND to GND −0.3 V to +0.3 V 16-lead TSSOP_EP 39.48 °C/W Operating Junction Temperature Range −40°C to +125°C θJA is specified for the worst-case conditions, that is, a device Storage Temperature Range −65°C to +150°C soldered in circuit board (4-layer, JEDEC standard board) for Soldering Conditions JEDEC J-STD-020 surface-mount packages. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
ESD CAUTION
rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 5 of 28 Document Outline Features Applications Typical Applications Circuit General Description Revision History Specifications Absolute Maximum Ratings Thermal Information ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Functional Block Diagram Theory of Operation Control Scheme Internal Regulator (VREG) Bootstrap Circuitry Low-Side Driver Oscillator Synchronization Enable and Soft Start Power Good Peak Current-Limit and Short-Circuit Protection Overvoltage Protection (OVP) Undervoltage Lockout (UVLO) Thermal Shutdown Applications Information Input Capacitor Selection Output Voltage Setting Voltage Conversion Limitations Inductor Selection Output Capacitor Selection Low-Side Power Device Selection Programming Input Voltage UVLO Compensation Design Compensation Network Between COMP and GND Compensation Network Between COMP and FB ADIsimPower Design Tool Design Example Output Voltage Setting Frequency Setting Inductor Selection Output Capacitor Selection Low-Side MOSFET Selection Compensation Components Soft Start Time Program Input Capacitor Selection Recommended External Components Circuit Board Layout Recommendations Typical Applications Circuits Outline Dimensions Ordering Guide