Datasheet ADP5041 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | Micro PMU with 1.2 A Buck, Two 300 mA LDOs, Supervisory, Watchdog, and Manual Reset |
| 页数 / 页 | 40 / 1 — Micro PMU with 1.2 A Buck, Two 300 mA LDOs,. Supervisory, Watchdog, and … |
| 修订版 | B |
| 文件格式/大小 | PDF / 3.7 Mb |
| 文件语言 | 英语 |
Micro PMU with 1.2 A Buck, Two 300 mA LDOs,. Supervisory, Watchdog, and Manual Reset. Data Sheet. ADP5041. FEATURES
文件文字版本
Micro PMU with 1.2 A Buck, Two 300 mA LDOs, Supervisory, Watchdog, and Manual Reset Data Sheet ADP5041 FEATURES FUNCTIONAL BLOCK DIAGRAM Input voltage range: 2.3 V to 5.5 V VOUT1 RFILT = 30Ω AVIN L1 One 1.2 A buck regulator 1µH SW VOUT1 AT 1.2A Two 300 mA LDOs FB1 BUCK R1 VBIAS C6 10µF R2 20-lead, 4 mm × 4 mm LFCSP package V VIN1 IN1 = 2.3V TO 5.5V C1 PGND Overcurrent and thermal protection 4.7µF EN_BK ON FPWM MODE OFF EN1 PSM/PWM Soft start VOUT2 LDO1 VOUT2 AT V VIN2 IN2 = 1.7V (DIGITAL) 300mA Undervoltage lockout FB2 R3 TO 5.5V C2 EN_LDO1 C5 1µF R4 2.2µF Open-drain processor reset with externally adjustable ON EN2 OFF threshold monitoring nRSTO VBIAS µP Guaranteed reset output valid to V MR WDI AVIN = 1 V SUPERVISOR VTHR Manual reset input ON EN3 R4 R5 OFF Watchdog refresh input EN_LDO2 VOUT3 Buck key specifications VIN3 V V IN3 = 1.7V LDO2 OUT3 AT TO 5.5V (ANALOG) FB3 300mA C3 Output voltage range: 0.8 V to 3.8 V 1µF C6 R7 R3 2.2µF
01
Current mode topology for excellent transient response AGND
0 2- 65 09
3 MHz operating frequency
Figure 1.
Peak efficiency up to 96% Uses tiny multilayer inductors and capacitors Mode pin selects forced PWM or auto PWM/PSM mode 100% duty cycle low dropout mode LDOs key specifications Output voltage range: 0.8 V to 5.2 V Low input supply voltage from 1.7 V to 5.5 V Stable with 2.2 μF ceramic output capacitors High PSRR Low output noise Low dropout voltage −40°C to +125°C junction temperature range GENERAL DESCRIPTION
The ADP5041 combines one high performance buck regulator range of the ADP5041 LDOs extend the battery life of portable and two low dropout (LDO) regulators in a small 20-lead devices. The ADP5041 LDOs maintain a power supply rejection LFCSP to meet demanding performance and board space greater than 60 dB for frequencies as high as 10 kHz while requirements. operating with a low headroom voltage. The high switching frequency of the buck regulator enables Each regulator in the ADP5041 is activated by a high level on use of tiny multilayer external components and minimizes the respective enable pin. The output voltages of the regulators board space. and the reset threshold are programmed through external resistor When the MODE pin is set to logic high, the buck regulator dividers to address a variety of applications. The ADP5041 operates in forced PWM mode. When the MODE pin is set to contains supervisory circuits that monitor power supply voltage logic low, the buck regulator operates in PWM mode when the levels and code execution integrity in microprocessor-based load is around the nominal value. When the load current falls systems. They also provide power-on reset signals. An on-chip below a predefined threshold, the regulator operates in power watchdog timer can reset the microprocessor if it fails to strobe save mode (PSM), improving the light load efficiency. The low within a preset timeout period. quiescent current, low dropout voltage, and wide input voltage
Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2011–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS GENERAL SPECIFICATIONS SUPERVISORY SPECIFICATIONS BUCK SPECIFICATIONS LDO1, LDO2 SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER MANAGEMENT UNIT Thermal Protection Undervoltage Lockout Enable/Shutdown Active Pull-Down BUCK SECTION Control Scheme PWM Mode Power Save Mode (PSM) PSM Current Threshold Short-Circuit Protection Soft Start Current Limit 100% Duty Operation LDO SECTION SUPERVISORY SECTION Reset Output Manual Reset Input Watchdog Input APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Feedback Resistors Inductor Output Capacitor Input Capacitor LDO EXTERNAL COMPONENT SELECTION Feedback Resistors OUTPUT CAPACITOR Input Bypass Capacitor Input and Output Capacitor Properties SUPERVISORY SECTION Threshold Setting Resistors Watchdog Input Current Negative-Going Transients at the Monitored Rail Watchdog Software Considerations POWER DISSIPATION/THERMAL CONSIDERATIONS Buck Regulator Power Dissipation LDO Regulator Power Dissipation Junction Temperature APPLICATION DIAGRAM PCB LAYOUT GUIDELINES SUGGESTED LAYOUT BILL OF MATERIALS FACTORY PROGRAMMABLE OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
01
Current mode topology for excellent transient response AGND
0 2- 65 09
3 MHz operating frequency
Figure 1.
Peak efficiency up to 96% Uses tiny multilayer inductors and capacitors Mode pin selects forced PWM or auto PWM/PSM mode 100% duty cycle low dropout mode LDOs key specifications Output voltage range: 0.8 V to 5.2 V Low input supply voltage from 1.7 V to 5.5 V Stable with 2.2 μF ceramic output capacitors High PSRR Low output noise Low dropout voltage −40°C to +125°C junction temperature range GENERAL DESCRIPTION
The ADP5041 combines one high performance buck regulator range of the ADP5041 LDOs extend the battery life of portable and two low dropout (LDO) regulators in a small 20-lead devices. The ADP5041 LDOs maintain a power supply rejection LFCSP to meet demanding performance and board space greater than 60 dB for frequencies as high as 10 kHz while requirements. operating with a low headroom voltage. The high switching frequency of the buck regulator enables Each regulator in the ADP5041 is activated by a high level on use of tiny multilayer external components and minimizes the respective enable pin. The output voltages of the regulators board space. and the reset threshold are programmed through external resistor When the MODE pin is set to logic high, the buck regulator dividers to address a variety of applications. The ADP5041 operates in forced PWM mode. When the MODE pin is set to contains supervisory circuits that monitor power supply voltage logic low, the buck regulator operates in PWM mode when the levels and code execution integrity in microprocessor-based load is around the nominal value. When the load current falls systems. They also provide power-on reset signals. An on-chip below a predefined threshold, the regulator operates in power watchdog timer can reset the microprocessor if it fails to strobe save mode (PSM), improving the light load efficiency. The low within a preset timeout period. quiescent current, low dropout voltage, and wide input voltage
Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2011–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS GENERAL SPECIFICATIONS SUPERVISORY SPECIFICATIONS BUCK SPECIFICATIONS LDO1, LDO2 SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER MANAGEMENT UNIT Thermal Protection Undervoltage Lockout Enable/Shutdown Active Pull-Down BUCK SECTION Control Scheme PWM Mode Power Save Mode (PSM) PSM Current Threshold Short-Circuit Protection Soft Start Current Limit 100% Duty Operation LDO SECTION SUPERVISORY SECTION Reset Output Manual Reset Input Watchdog Input APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Feedback Resistors Inductor Output Capacitor Input Capacitor LDO EXTERNAL COMPONENT SELECTION Feedback Resistors OUTPUT CAPACITOR Input Bypass Capacitor Input and Output Capacitor Properties SUPERVISORY SECTION Threshold Setting Resistors Watchdog Input Current Negative-Going Transients at the Monitored Rail Watchdog Software Considerations POWER DISSIPATION/THERMAL CONSIDERATIONS Buck Regulator Power Dissipation LDO Regulator Power Dissipation Junction Temperature APPLICATION DIAGRAM PCB LAYOUT GUIDELINES SUGGESTED LAYOUT BILL OF MATERIALS FACTORY PROGRAMMABLE OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE