Datasheet ADP2164 (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | 6.5V, 4 A, High Efficiency, Step-Down DC-to-DC Regulator |
| 页数 / 页 | 19 / 3 — Data Sheet. ADP2164. SPECIFICATIONS. Table 1. Parameter. Symbol. Test … |
| 修订版 | C |
| 文件格式/大小 | PDF / 751 Kb |
| 文件语言 | 英语 |
Data Sheet. ADP2164. SPECIFICATIONS. Table 1. Parameter. Symbol. Test Conditions/Comments. Min. Typ. Max. Unit
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Data Sheet ADP2164 SPECIFICATIONS
VIN = PVIN = 3.3 V, EN high, SYNC high, TJ = −40°C to +125°C, unless otherwise noted. Typical values are at TJ = 25°C.
Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
VIN AND PVIN PINS VIN Voltage Range VIN 2.7 6.5 V PVIN Voltage Range PVIN 2.7 6.5 V Quiescent Current IVIN No switching 895 1100 µA Shutdown Current ISHDN VIN = PVIN = 6.5 V, EN = GND 9 12 µA VIN Undervoltage Lockout Threshold UVLO VIN rising 2.6 2.7 V VIN falling 2.4 2.5 V OUTPUT CHARACTERISTICS Specified by the circuit in Figure 42 Load Regulation IO = 0 A to 4 A 0.05 %/A Line Regulation IO = 2 A 0.05 %/V FB PIN FB Regulation Voltage VFB TJ = −40°C to +125°C 0.591 0.6 0.609 V FB Bias Current IFB 0.01 0.1 µA SW PIN High-Side On Resistance1 VIN = PVIN = 3.3 V, ISW = 500 mA 35 52 70 mΩ VIN = PVIN = 5 V, ISW = 500 mA 30 43 55 mΩ Low-Side On Resistance1 VIN = PVIN = 3.3 V, ISW = 500 mA 24 32 40 mΩ VIN = PVIN = 5 V, ISW = 500 mA 20 29 35 mΩ SW Peak Current Limit High-side switch, PVIN = 3.3 V 5 6.2 7.4 A SW Maximum Duty Cycle Full frequency 100 % SW Minimum On Time2 Full frequency 100 ns TRK PIN TRK Input Voltage Range 0 600 mV TRK to FB Offset Voltage TRK = 0 mV to 500 mV −15 +15 mV TRK Input Bias Current 100 nA FREQUENCY Switching Frequency fS RT = VIN 1.08 1.2 1.32 MHz RT = GND 540 600 660 kHz RT = 91 kΩ 480 600 720 kHz Switching Frequency Range 500 1400 kHz RT Pin Input High Voltage 1.2 V RT Pin Input Low Voltage 0.45 V SYNC PIN Synchronization Range 0.5 1.4 MHz Minimum Pulse Width 100 ns Minimum Off Time 100 ns Input High Voltage 1.2 V Input Low Voltage 0.4 V PGOOD PIN Power-Good Range FB rising threshold 105 110 115 % FB rising hysteresis 2.5 % FB falling threshold 85 90 95 % FB falling hysteresis 2.5 % Power-Good Deglitch Time From FB to PGOOD 16 Clock cycles Power-Good Leakage Current VPGOOD = 5 V 0.1 1 µA Power-Good Output Low Voltage IPGOOD = 1 mA 170 220 mV Rev. C | Page 3 of 19 Document Outline Features Applications Typical Applications Circuit General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Functional Block Diagram Theory of Operation Control Scheme Slope Compensation Precision Enable/Shutdown Integrated Soft Start Oscillator and Synchronization Power Good Current Limit and Short-Circuit Protection Overvoltage Protection (OVP) Undervoltage Lockout (UVLO) Thermal Shutdown Applications Information ADIsimPower Design Tool Output Voltage Selection Inductor Selection Output Capacitor Selection Input Capacitor Selection Voltage Tracking Coincident Tracking Ratiometric Tracking Applications Circuits Outline Dimensions Ordering Guide
Data Sheet ADP2164 SPECIFICATIONS
VIN = PVIN = 3.3 V, EN high, SYNC high, TJ = −40°C to +125°C, unless otherwise noted. Typical values are at TJ = 25°C.
Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
VIN AND PVIN PINS VIN Voltage Range VIN 2.7 6.5 V PVIN Voltage Range PVIN 2.7 6.5 V Quiescent Current IVIN No switching 895 1100 µA Shutdown Current ISHDN VIN = PVIN = 6.5 V, EN = GND 9 12 µA VIN Undervoltage Lockout Threshold UVLO VIN rising 2.6 2.7 V VIN falling 2.4 2.5 V OUTPUT CHARACTERISTICS Specified by the circuit in Figure 42 Load Regulation IO = 0 A to 4 A 0.05 %/A Line Regulation IO = 2 A 0.05 %/V FB PIN FB Regulation Voltage VFB TJ = −40°C to +125°C 0.591 0.6 0.609 V FB Bias Current IFB 0.01 0.1 µA SW PIN High-Side On Resistance1 VIN = PVIN = 3.3 V, ISW = 500 mA 35 52 70 mΩ VIN = PVIN = 5 V, ISW = 500 mA 30 43 55 mΩ Low-Side On Resistance1 VIN = PVIN = 3.3 V, ISW = 500 mA 24 32 40 mΩ VIN = PVIN = 5 V, ISW = 500 mA 20 29 35 mΩ SW Peak Current Limit High-side switch, PVIN = 3.3 V 5 6.2 7.4 A SW Maximum Duty Cycle Full frequency 100 % SW Minimum On Time2 Full frequency 100 ns TRK PIN TRK Input Voltage Range 0 600 mV TRK to FB Offset Voltage TRK = 0 mV to 500 mV −15 +15 mV TRK Input Bias Current 100 nA FREQUENCY Switching Frequency fS RT = VIN 1.08 1.2 1.32 MHz RT = GND 540 600 660 kHz RT = 91 kΩ 480 600 720 kHz Switching Frequency Range 500 1400 kHz RT Pin Input High Voltage 1.2 V RT Pin Input Low Voltage 0.45 V SYNC PIN Synchronization Range 0.5 1.4 MHz Minimum Pulse Width 100 ns Minimum Off Time 100 ns Input High Voltage 1.2 V Input Low Voltage 0.4 V PGOOD PIN Power-Good Range FB rising threshold 105 110 115 % FB rising hysteresis 2.5 % FB falling threshold 85 90 95 % FB falling hysteresis 2.5 % Power-Good Deglitch Time From FB to PGOOD 16 Clock cycles Power-Good Leakage Current VPGOOD = 5 V 0.1 1 µA Power-Good Output Low Voltage IPGOOD = 1 mA 170 220 mV Rev. C | Page 3 of 19 Document Outline Features Applications Typical Applications Circuit General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Functional Block Diagram Theory of Operation Control Scheme Slope Compensation Precision Enable/Shutdown Integrated Soft Start Oscillator and Synchronization Power Good Current Limit and Short-Circuit Protection Overvoltage Protection (OVP) Undervoltage Lockout (UVLO) Thermal Shutdown Applications Information ADIsimPower Design Tool Output Voltage Selection Inductor Selection Output Capacitor Selection Input Capacitor Selection Voltage Tracking Coincident Tracking Ratiometric Tracking Applications Circuits Outline Dimensions Ordering Guide