Datasheet ADP5023 (Analog Devices) - 5

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Data Sheet ADP5023 LDO SPECIFICATIONS
VIN3 = (VOUT3 + 0.5 V) or 1.7 V (whichever is greater) to 5.5 V; CIN = COUT = 1 µF; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.1
Table 4. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE RANGE VIN3 1.7 5.5 V OPERATING SUPPLY CURRENT Bias Current per LDO2 IVIN3BIAS IOUT3 = 0 µA 10 30 µA IOUT3 = 10 mA 60 100 µA IOUT3 = 300 mA 165 245 µA Total System Input Current IIN Includes all current into AVIN, VIN1, VIN2, and VIN3 LDO Only IOUT3 = 0 µA, all other channels disabled 53 µA OUTPUT CHARACTERISTICS Output Voltage Accuracy ΔVOUT3/VOUT3 100 µA < IOUT3 < 300 mA −1.8 +1.8 % Line Regulation (ΔVOUT3/VOUT3)/ΔVIN3 IOUT3 = 1 mA −0.03 +0.03 %/V Load Regulation3 (ΔVOUT3/VOUT3)/ΔIOUT3 IOUT3 = 1 mA to 300 mA 0.001 0.003 %/mA VOLTAGE FEEDBACK VFB3 0.491 0.5 0.509 V DROPOUT VOLTAGE4 VDROPOUT VOUT3 = 5.2 V, IOUT3 = 300 mA 50 mV VOUT3 = 3.3 V, IOUT3 = 300 mA 75 140 mV VOUT3 = 2.5 V, IOUT3 = 300 mA 100 mV VOUT3 = 1.8 V, IOUT3 = 300 mA 180 mV CURRENT-LIMIT THRESHOLD5 ILIMIT3 335 600 mA ACTIVE PULL-DOWN RPDWN-L Channel disabled 600 Ω OUTPUT NOISE Regulator LDO NOISELDO 10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 2.8 V 100 µV rms POWER SUPPLY REJECTION PSRR RATIO Regulator LDO 10 kHz, VIN3 = 3.3 V, VOUT3 = 2.8 V, IOUT3 = 1 mA 60 dB 100 kHz, VIN3 = 3.3 V, VOUT3 = 2.8 V, IOUT3 = 1 mA 62 dB 1 MHz, VIN3 = 3.3 V, VOUT3 = 2.8 V, IOUT3 = 1 mA 63 dB 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2 This is the input current into VIN3, which is not delivered to the output load. 3 Based on an endpoint calculation using 1 mA and 300 mA loads. 4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages above 1.7 V. 5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
TA = −40°C to +125°C, unless otherwise specified.
Table 5. Parameter Symbol Min Typ Max Unit
NOMINAL INPUT AND OUTPUT CAPACITOR RATINGS BUCK1, BUCK2 Input Capacitor Ratings CMIN1, CMIN2 4.7 40 µF BUCK1, BUCK2 Output Capacitor Ratings CMIN1, CMIN2 10 40 µF LDO1 Input and Output Capacitor Ratings CMIN3, CMIN4 1.0 µF CAPACITOR ESR RESR 0.001 1 Ω 1 The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use because of their poor temperature and dc bias characteristics. Rev. D | Page 5 of 28 Document Outline Features Applications General Description Typical Application Circuit Revision History Specifications General Specifications BUCK1 and BUCK2 Specifications LDO Specifications Input and Output Capacitor, Recommended Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Power Management Unit Thermal Protection Undervoltage Lockout Enable/Shutdown BUCK1 and BUCK2 Control Scheme PWM Mode Power Save Mode (PSM) PSM Current Threshold Oscillator/Phasing of Inductor Switching Short-Circuit Protection Soft Start Current Limit 100% Duty Operation Active Pull-Downs LDO Applications Information Buck External Component Selection Feedback Resistors Inductor Output Capacitor Input Capacitor LDO External Component Selection Feedback Resistors Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties Power Dissipation and Thermal Considerations Buck Regulator Power Dissipation LDO Regulator Power Dissipation Junction Temperature PCB Layout Guidelines Typical Application Schematics Bill of Materials Outline Dimensions Ordering Guide