Datasheet ADP5033 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | Dual 3 MHz, 800 mA Buck Regulators with Two 300 mA LDOs |
| 页数 / 页 | 28 / 1 — Dual 3 MHz, 800 mA Buck. Regulators with Two 300 mA LDOs. Data Sheet. … |
| 修订版 | H |
| 文件格式/大小 | PDF / 831 Kb |
| 文件语言 | 英语 |
Dual 3 MHz, 800 mA Buck. Regulators with Two 300 mA LDOs. Data Sheet. ADP5033. FEATURES. TYPICAL APPLICATION CIRCUIT
文件文字版本
Dual 3 MHz, 800 mA Buck Regulators with Two 300 mA LDOs Data Sheet ADP5033 FEATURES TYPICAL APPLICATION CIRCUIT Main input voltage range: 2.3 V to 5.5 V ADP5033 Two 800 mA buck regulators and two 300 mA LDOs L1 1µH VOUT1 2.3V SW1 VIN1 @ Tiny, 16-ball, 2 mm × 2 mm WLCSP package TO VOUT1 800mA 5.5V C1 BUCK1 4.7µF C5 Regulator accuracy: ±1.8% PGND1 10µF EN1 Factory programmable VOUTx ENA MODE O . AND 3 MHz buck operation with forced PWM and auto PWM/PSM L ON IV EN2 OFF ENB UV EN3 PWM modes MODE ACT EN4 PSM/PWM BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V VIN2 MODE L2 1µH C2 SW2 VOUT2 LDO1/LDO2: output voltage range from 0.8 V to 5.2 V 4.7µF @ BUCK2 VOUT2 800mA LDO1/LDO2: low input supply voltage from 1.7 V to 5.5 V C6 EN2 PGND2 10µF LDO1/LDO2: high PSRR and low output noise EN3 APPLICATIONS 1.7V VIN3 VOUT3 VOUT3 TO LDO1 @ 5.5V C3 (ANALOG) 300mA Power for processors, ASICS, FPGAs, and RF chipsets 1µF C7 1µF Portable instrumentation and medical devices EN4 VIN4 VOUT4 VOUT4 Space constrained devices LDO2 @ C4 (DIGITAL) 300mA 1µF C8 1µF
001
AGND
09788- Figure 1.
GENERAL DESCRIPTION
The ADP5033 combines two high performance buck regulators The regulators in the ADP5033 are activated by the ENA and ENB and two low dropout regulators (LDO) in a tiny, 16-ball, 2 mm × pins. The specific channels controlled by ENA and ENB are set 2 mm WLCSP to meet demanding performance and board space by factory programming. A high voltage level applied to the enable requirements. pins activates the regulators. The default output voltages are The high switching frequency of the buck regulators enables tiny factory programmable and can be set to a wide range of options. multilayer external components and minimizes the board space.
Table 1. Family Models
When the MODE pin is set high, the buck regulators operate in
Maximum
forced PWM mode. When the MODE pin is set low, the buck
Model Channels Current Package
regulators operate in PWM mode when the load current is above ADP5023 2 Bucks, 1 LDO 800 mA, 300 mA LFCSP (CP-24-10) a predefined threshold. When the load current falls below a ADP5024 2 Bucks, 1 LDO 1.2 A, 300 mA LFCSP (CP-24-10) predefined threshold, the regulator operates in power save ADP5034 2 Bucks, 2 LDOs 1.2 A, 300 mA LFCSP (CP-24-10), mode (PSM), improving the light load efficiency. TSSOP (RE-28-1) ADP5037 2 Bucks, 2 LDOs 800 mA, 300 mA LFCSP (CP-24-10) The two bucks operate out of phase to reduce the input capacitor ADP5033 2 Bucks, 2 LDOs with 800 mA, 300 mA WLCSP (CB-16-8) requirement and noise. 2 EN pins ADP5040 1 Buck, 2 LDOs 1.2 A, 300 mA LFCSP (CP-20-10) The low quiescent current, low dropout voltage, and wide input ADP5041 1 Buck, 2 LDOs with 1.2 A, 300 mA LFCSP (CP-20-10) voltage range of the ADP5033 LDO extend the battery life of Supervisory, Watchdog, portable devices. The ADP5033 LDOs maintain power supply Manual Reset rejection greater than 60 dB for frequencies as high as 10 kHz ADP5133 2 Bucks with 2 ENx pins 800 mA WLCSP (CB-16-8) while operating with a low headroom voltage. ADP5134 2 Bucks, 2 LDOs with 1.2 A, 300 mA LFCSP (CP-24-10) precision enable and power-good output
Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2011–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Features Applications Typical Application Circuit General Description Table of Contents Revision History Specifications General Specifications BUCK1 and BUCK2 Specifications LDO1 and LDO2 Specifications Input and Output Capacitor, Recommended Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Power Management Unit Thermal Protection Undervoltage Lockout Enable/Shutdown BUCK1 and BUCK2 Control Scheme PWM Mode PSM PSM Current Threshold Oscillator/Phasing of Inductor Switching Short-Circuit Protection Soft Start Current Limit 100% Duty Operation Active Pull-Downs LDO1 and LDO2 Applications Information Buck External Component Selection Inductor Output Capacitor Input Capacitor LDO Capacitor Selection Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties Power Dissipation and Thermal Considerations Buck Regulator Power Dissipation LDO Regulator Power Dissipation Junction Temperature PCB Layout Guidelines Typical Application Schematic Outline Dimensions Ordering Guide
001
AGND
09788- Figure 1.
GENERAL DESCRIPTION
The ADP5033 combines two high performance buck regulators The regulators in the ADP5033 are activated by the ENA and ENB and two low dropout regulators (LDO) in a tiny, 16-ball, 2 mm × pins. The specific channels controlled by ENA and ENB are set 2 mm WLCSP to meet demanding performance and board space by factory programming. A high voltage level applied to the enable requirements. pins activates the regulators. The default output voltages are The high switching frequency of the buck regulators enables tiny factory programmable and can be set to a wide range of options. multilayer external components and minimizes the board space.
Table 1. Family Models
When the MODE pin is set high, the buck regulators operate in
Maximum
forced PWM mode. When the MODE pin is set low, the buck
Model Channels Current Package
regulators operate in PWM mode when the load current is above ADP5023 2 Bucks, 1 LDO 800 mA, 300 mA LFCSP (CP-24-10) a predefined threshold. When the load current falls below a ADP5024 2 Bucks, 1 LDO 1.2 A, 300 mA LFCSP (CP-24-10) predefined threshold, the regulator operates in power save ADP5034 2 Bucks, 2 LDOs 1.2 A, 300 mA LFCSP (CP-24-10), mode (PSM), improving the light load efficiency. TSSOP (RE-28-1) ADP5037 2 Bucks, 2 LDOs 800 mA, 300 mA LFCSP (CP-24-10) The two bucks operate out of phase to reduce the input capacitor ADP5033 2 Bucks, 2 LDOs with 800 mA, 300 mA WLCSP (CB-16-8) requirement and noise. 2 EN pins ADP5040 1 Buck, 2 LDOs 1.2 A, 300 mA LFCSP (CP-20-10) The low quiescent current, low dropout voltage, and wide input ADP5041 1 Buck, 2 LDOs with 1.2 A, 300 mA LFCSP (CP-20-10) voltage range of the ADP5033 LDO extend the battery life of Supervisory, Watchdog, portable devices. The ADP5033 LDOs maintain power supply Manual Reset rejection greater than 60 dB for frequencies as high as 10 kHz ADP5133 2 Bucks with 2 ENx pins 800 mA WLCSP (CB-16-8) while operating with a low headroom voltage. ADP5134 2 Bucks, 2 LDOs with 1.2 A, 300 mA LFCSP (CP-24-10) precision enable and power-good output
Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2011–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Features Applications Typical Application Circuit General Description Table of Contents Revision History Specifications General Specifications BUCK1 and BUCK2 Specifications LDO1 and LDO2 Specifications Input and Output Capacitor, Recommended Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Power Management Unit Thermal Protection Undervoltage Lockout Enable/Shutdown BUCK1 and BUCK2 Control Scheme PWM Mode PSM PSM Current Threshold Oscillator/Phasing of Inductor Switching Short-Circuit Protection Soft Start Current Limit 100% Duty Operation Active Pull-Downs LDO1 and LDO2 Applications Information Buck External Component Selection Inductor Output Capacitor Input Capacitor LDO Capacitor Selection Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties Power Dissipation and Thermal Considerations Buck Regulator Power Dissipation LDO Regulator Power Dissipation Junction Temperature PCB Layout Guidelines Typical Application Schematic Outline Dimensions Ordering Guide