Datasheet ADP2127 (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | Ultralow Profile, 500 mA, 6 MHz, Synchronous, Step-Down, DC-to-DC, EWLP |
| 页数 / 页 | 20 / 4 — ADP2126/ADP2127. Data Sheet. Parameter Symbol. Test. Conditions/Comments. … |
| 修订版 | B |
| 文件格式/大小 | PDF / 884 Kb |
| 文件语言 | 英语 |
ADP2126/ADP2127. Data Sheet. Parameter Symbol. Test. Conditions/Comments. Min. Typ. Max. Unit. TIMING DIAGRAMS. VIN × 90%. VIN. VIN × 10%. VOUT
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ADP2126/ADP2127 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit
TIMING See Figure 2 and Figure 3 VIN High to EXTCLK On2 t1 VIN = 2.1 V to 5.5 V 200 μs EXTCLK On to VOUT Rising t2 (CLOCK) DEXTCLK = 40% to 60%, fEXTCLK = 6 MHz 250 320 400 μs DEXTCLK = 40% to 60%, fEXTCLK = 27 MHz 250 320 400 μs EXTCLK On to VOUT Rising t2 (LOGIC) EXTCLK = logic high 285 315 385 μs VOUT Power-Up Time (Soft Start)2 t3 COUT = 2.2 μF, RLOAD = 3.6 Ω 70 200 μs EXTCLK Off to VOUT Falling t5 (CLOCK) DEXTCLK = 40% to 60%, fEXTCLK = 6 MHz to 27 MHz 9 17 μs EXTCLK Off to VOUT Falling t5 (LOGIC) EXTCLK = logic high, no load 0 μs VOUT Power-Down Time t6 COUT = 2.2 μF, RLOAD = 3.6 Ω 16 μs COUT = 2.2 μF, no load 465 μs Minimum Shutdown Time2 t5 + t6 COUT = 2.2 μF, no load 1400 μs Minimum Power-Off Time2 t7 500 μs 1 The total shutdown current is the addition of VIN shutdown current and SW leakage. 2 Guaranteed by design. 3 Transients not included in voltage accuracy specifications. 4 The PFM output voltage will be higher than the PWM output voltage. See the Typical Performance Characteristic sect s ion. 5 Thermal shutdown protection is only active in PWM mode.
TIMING DIAGRAMS VIN × 90% t VIN 7 VIN × 10% t6 t3 VOUT VOUT(NOM) × 10% t2 t5 EXTCLK
-003
t1
658 09 Figure 2. Clock Enable I/O Timing Diagram
VIN × 90% t VIN 7 VIN × 10% t6 t3 VOUT VOUT(NOM) × 10% t2 t5 EXTCLK
-004
t1
658 09 Figure 3. Logic Enable I/O Timing Diagram (Logic High Enable Feature Available Only on Certain Models) Rev. B | Page 4 of 20 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATIONS CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION OVERVIEW EXTERNAL CLOCK (EXTCLK) ENABLE SPREAD SPECTRUM OSCILLATOR MODE SELECTION Pulse-Width Modulation (PWM) Mode Auto Mode (PFM and PWM Switching) Pulse Frequency Modulation (PFM) Mode Mode Transition INTERNAL CONTROL FEATURES Synchronous Rectification Soft Start PROTECTION FEATURES Overcurrent Protection Output Short-Circuit Protection (SCP) Thermal Shutdown (TSD) Protection Undervoltage Lockout (UVLO) TIMING CONSTRAINTS Shutdown Time Power-Off Time APPLICATIONS INFORMATION INDUCTOR SELECTION INPUT CAPACITOR SELECTION OUTPUT CAPACITOR SELECTION THERMAL CONSIDERATIONS PCB LAYOUT GUIDELINES OUTLINE DIMENSIONS ORDERING GUIDE
ADP2126/ADP2127 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit
TIMING See Figure 2 and Figure 3 VIN High to EXTCLK On2 t1 VIN = 2.1 V to 5.5 V 200 μs EXTCLK On to VOUT Rising t2 (CLOCK) DEXTCLK = 40% to 60%, fEXTCLK = 6 MHz 250 320 400 μs DEXTCLK = 40% to 60%, fEXTCLK = 27 MHz 250 320 400 μs EXTCLK On to VOUT Rising t2 (LOGIC) EXTCLK = logic high 285 315 385 μs VOUT Power-Up Time (Soft Start)2 t3 COUT = 2.2 μF, RLOAD = 3.6 Ω 70 200 μs EXTCLK Off to VOUT Falling t5 (CLOCK) DEXTCLK = 40% to 60%, fEXTCLK = 6 MHz to 27 MHz 9 17 μs EXTCLK Off to VOUT Falling t5 (LOGIC) EXTCLK = logic high, no load 0 μs VOUT Power-Down Time t6 COUT = 2.2 μF, RLOAD = 3.6 Ω 16 μs COUT = 2.2 μF, no load 465 μs Minimum Shutdown Time2 t5 + t6 COUT = 2.2 μF, no load 1400 μs Minimum Power-Off Time2 t7 500 μs 1 The total shutdown current is the addition of VIN shutdown current and SW leakage. 2 Guaranteed by design. 3 Transients not included in voltage accuracy specifications. 4 The PFM output voltage will be higher than the PWM output voltage. See the Typical Performance Characteristic sect s ion. 5 Thermal shutdown protection is only active in PWM mode.
TIMING DIAGRAMS VIN × 90% t VIN 7 VIN × 10% t6 t3 VOUT VOUT(NOM) × 10% t2 t5 EXTCLK
-003
t1
658 09 Figure 2. Clock Enable I/O Timing Diagram
VIN × 90% t VIN 7 VIN × 10% t6 t3 VOUT VOUT(NOM) × 10% t2 t5 EXTCLK
-004
t1
658 09 Figure 3. Logic Enable I/O Timing Diagram (Logic High Enable Feature Available Only on Certain Models) Rev. B | Page 4 of 20 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATIONS CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION OVERVIEW EXTERNAL CLOCK (EXTCLK) ENABLE SPREAD SPECTRUM OSCILLATOR MODE SELECTION Pulse-Width Modulation (PWM) Mode Auto Mode (PFM and PWM Switching) Pulse Frequency Modulation (PFM) Mode Mode Transition INTERNAL CONTROL FEATURES Synchronous Rectification Soft Start PROTECTION FEATURES Overcurrent Protection Output Short-Circuit Protection (SCP) Thermal Shutdown (TSD) Protection Undervoltage Lockout (UVLO) TIMING CONSTRAINTS Shutdown Time Power-Off Time APPLICATIONS INFORMATION INDUCTOR SELECTION INPUT CAPACITOR SELECTION OUTPUT CAPACITOR SELECTION THERMAL CONSIDERATIONS PCB LAYOUT GUIDELINES OUTLINE DIMENSIONS ORDERING GUIDE