Datasheet LT3688 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | Dual 800mA Step-Down Switching Regulator with Power-On Reset and Watchdog Timer |
| 页数 / 页 | 28 / 8 — PIN FUNCTIONS (QFN/TSSOP). RT (Pin 1/Pin 22):. CONFIG (Pin 10/Pin 7):. … |
| 文件格式/大小 | PDF / 430 Kb |
| 文件语言 | 英语 |
PIN FUNCTIONS (QFN/TSSOP). RT (Pin 1/Pin 22):. CONFIG (Pin 10/Pin 7):. SYNC (Pin 2/Pin 23):. EN/UVLO (Pin 3/Pin 24):
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文件文字版本
LT3688
PIN FUNCTIONS (QFN/TSSOP) RT (Pin 1/Pin 22):
The RT pin is used to set the internal
CONFIG (Pin 10/Pin 7):
The CONFIG pin programs the oscillator frequency. Tie a resistor from RT to GND to set start-up sequence of the two voltage regulators and the the switching frequency. behavior of the power-on reset and watchdog timers. To select one of three confi guration options, tie the CONFIG pin
SYNC (Pin 2/Pin 23):
Drive the SYNC pin with a logic- to V level signal with positive and negative pulse widths of at IN, tie the CONFIG pin to GND or leave the CONFIG pin fl oating. With the CONFIG pin tied to V least 150ns. Do not fl oat this pin. Tie to GND if the SYNC IN, each reset output depends on its respective FB pin. Channel 2 only starts when feature is not used. FB1 rises above 0.72V, and the watchdog timer only starts
EN/UVLO (Pin 3/Pin 24):
The EN/UVLO pin is used to put when both RST pins go high. With the CONFIG pin tied to the LT3688 in shutdown mode. Pull the pin below 0.3V to GND, both RST pins pull low until both FB pins rise above shut down the LT3688. The 1.25V threshold can function 0.72V and the POR timer programmed by CPOR1 expires. as an accurate undervoltage lockout (UVLO), preventing Again, channel 2 only starts when FB1 rises above 0.72V, the regulator from operating until the input voltage has and the watchdog timer only starts when both RST pins go reached the programmed level. high. Tie CPOR2 to GND if the CONFIG pin is tied low. With
FB1, FB2 (Pins 4, 15/Pins 1, 12):
The LT3688 regulates the CONFIG pin fl oating, both channels start coincidentally, the feedback pins to 0.800V. Connect the feedback resistor each reset output depends on its respective FB pin, and the divider taps to this pin. watchdog timer starts when RST1 goes high.
RUN/SS1, RUN/SS2 (Pins 5, 14/Pins 2, 11):
Place a
RST1, RST2 (Pins 17, 16/Pins 14, 13):
The RST pins are capacitor from RUN/SS to GND to program the soft start active low, open-drain logic outputs with a weak pull-up to period. Use a 1000pF or larger capacitor at these pins. To BIAS. After VFB rises above 0.72V, the reset remains asserted ensure the SS capacitors are discharged, internal circuitry for the period set by the capacitor on the CPOR pin. Tie the pulls the RUN/SS pins low and disables switching during RST pins to BIAS with a 100k resistor for a stronger pull-up. startup before initiating the soft-start sequence. Once
WDO (Pin 18/Pin 15):
WDO will go low if the micropro- the RUN/SS pins fall below 0.2V, the pull down turns off, cessor fails to drive the WDI pin of the LT3688 with the the SS capacitors start charging again, and switching is appropriate signal. Tie the WDO pin to BIAS with a 100k enabled. Do not drive these pins directly. Use an open resistor for a stronger pull-up. Keep capacitive loading on drain or collector to pull them low, if necessary. this pin below 1000pF.
BST1, BST2 (Pins 6, 13/Pins 3, 10):
The BST pins are
WDE (Pin 19/Pin 16):
The watchdog timer enable pin used to provide drive voltage, higher than the input volt- disables the watchdog timer if the WDE voltage exceeds age, to the internal NPN power switches. 1V. Float this pin or tie to ground for normal operation.
SW1, SW2 (Pins 7, 12/Pins 4, 9):
The SW pins are the
WDI (Pin 20/Pin 17):
The watchdog timer input pin outputs of the internal power switches. Connect these receives the watchdog signal from the microprocessor. pins to the inductors, catch diodes and boost capacitors. If two or more negative edges occur on WDI before the
DA1, DA2 (Pins 8, 11/Pins 5, 8):
Tie the DA pin to the programmed fast timer period or no negative edge occurs anode of the external catch Schottky diode. If the DA pin within the slow timer period, the part will pulse WDO low current exceeds 1.2A, which could occur in an overload with a pulse width of 1/8th of the slow timer period. Drive or short-circuit condition, switching is disabled until the the WDI pin with a pulse width of at least 300ns. DA pin current falls below 1.2A.
BIAS (Pin 22/Pin 19):
The BIAS pin supplies current to the
V
internal circuitry when BIAS is above 3V, helping reduce
IN (Pin 9/Pin 6):
The VIN pin supplies current to the LT3688’s internal circuitry and to the internal power input quiescent current. The internal Schottky diodes are switches and must be locally bypassed. connected from BIAS to BST, providing the charging path for the boost capacitors. 3688f 8
PIN FUNCTIONS (QFN/TSSOP) RT (Pin 1/Pin 22):
The RT pin is used to set the internal
CONFIG (Pin 10/Pin 7):
The CONFIG pin programs the oscillator frequency. Tie a resistor from RT to GND to set start-up sequence of the two voltage regulators and the the switching frequency. behavior of the power-on reset and watchdog timers. To select one of three confi guration options, tie the CONFIG pin
SYNC (Pin 2/Pin 23):
Drive the SYNC pin with a logic- to V level signal with positive and negative pulse widths of at IN, tie the CONFIG pin to GND or leave the CONFIG pin fl oating. With the CONFIG pin tied to V least 150ns. Do not fl oat this pin. Tie to GND if the SYNC IN, each reset output depends on its respective FB pin. Channel 2 only starts when feature is not used. FB1 rises above 0.72V, and the watchdog timer only starts
EN/UVLO (Pin 3/Pin 24):
The EN/UVLO pin is used to put when both RST pins go high. With the CONFIG pin tied to the LT3688 in shutdown mode. Pull the pin below 0.3V to GND, both RST pins pull low until both FB pins rise above shut down the LT3688. The 1.25V threshold can function 0.72V and the POR timer programmed by CPOR1 expires. as an accurate undervoltage lockout (UVLO), preventing Again, channel 2 only starts when FB1 rises above 0.72V, the regulator from operating until the input voltage has and the watchdog timer only starts when both RST pins go reached the programmed level. high. Tie CPOR2 to GND if the CONFIG pin is tied low. With
FB1, FB2 (Pins 4, 15/Pins 1, 12):
The LT3688 regulates the CONFIG pin fl oating, both channels start coincidentally, the feedback pins to 0.800V. Connect the feedback resistor each reset output depends on its respective FB pin, and the divider taps to this pin. watchdog timer starts when RST1 goes high.
RUN/SS1, RUN/SS2 (Pins 5, 14/Pins 2, 11):
Place a
RST1, RST2 (Pins 17, 16/Pins 14, 13):
The RST pins are capacitor from RUN/SS to GND to program the soft start active low, open-drain logic outputs with a weak pull-up to period. Use a 1000pF or larger capacitor at these pins. To BIAS. After VFB rises above 0.72V, the reset remains asserted ensure the SS capacitors are discharged, internal circuitry for the period set by the capacitor on the CPOR pin. Tie the pulls the RUN/SS pins low and disables switching during RST pins to BIAS with a 100k resistor for a stronger pull-up. startup before initiating the soft-start sequence. Once
WDO (Pin 18/Pin 15):
WDO will go low if the micropro- the RUN/SS pins fall below 0.2V, the pull down turns off, cessor fails to drive the WDI pin of the LT3688 with the the SS capacitors start charging again, and switching is appropriate signal. Tie the WDO pin to BIAS with a 100k enabled. Do not drive these pins directly. Use an open resistor for a stronger pull-up. Keep capacitive loading on drain or collector to pull them low, if necessary. this pin below 1000pF.
BST1, BST2 (Pins 6, 13/Pins 3, 10):
The BST pins are
WDE (Pin 19/Pin 16):
The watchdog timer enable pin used to provide drive voltage, higher than the input volt- disables the watchdog timer if the WDE voltage exceeds age, to the internal NPN power switches. 1V. Float this pin or tie to ground for normal operation.
SW1, SW2 (Pins 7, 12/Pins 4, 9):
The SW pins are the
WDI (Pin 20/Pin 17):
The watchdog timer input pin outputs of the internal power switches. Connect these receives the watchdog signal from the microprocessor. pins to the inductors, catch diodes and boost capacitors. If two or more negative edges occur on WDI before the
DA1, DA2 (Pins 8, 11/Pins 5, 8):
Tie the DA pin to the programmed fast timer period or no negative edge occurs anode of the external catch Schottky diode. If the DA pin within the slow timer period, the part will pulse WDO low current exceeds 1.2A, which could occur in an overload with a pulse width of 1/8th of the slow timer period. Drive or short-circuit condition, switching is disabled until the the WDI pin with a pulse width of at least 300ns. DA pin current falls below 1.2A.
BIAS (Pin 22/Pin 19):
The BIAS pin supplies current to the
V
internal circuitry when BIAS is above 3V, helping reduce
IN (Pin 9/Pin 6):
The VIN pin supplies current to the LT3688’s internal circuitry and to the internal power input quiescent current. The internal Schottky diodes are switches and must be locally bypassed. connected from BIAS to BST, providing the charging path for the boost capacitors. 3688f 8