Datasheet ADP2140 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 3 MHz, 600 mA, Low Quiescent Current Buck with 300 mA LDO Regulator |
| 页数 / 页 | 32 / 6 — ADP2140. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. PGND. … |
| 修订版 | A |
| 文件格式/大小 | PDF / 2.8 Mb |
| 文件语言 | 英语 |
ADP2140. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. PGND. VIN1. 2 ADP2140 9. AGND. TOP VIEW. EN1. (Not to Scale). EN2. VIN2
该数据表的模型线
文件文字版本
ADP2140 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PGND 1 10 VIN1 SW 2 ADP2140 9 PG AGND 3 TOP VIEW 8 EN1 (Not to Scale) FB 4 7 EN2 VIN2 5 6 VOUT2 NOTES 1. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP PACKAGE ENHANCES THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GROUND
3
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD BE
-00
CONNECTED TO THE GROUND PLANE ON THE CIRCUIT BOARD.
932 07 Figure 3. Pin Configuration
Table 5. Pin Function Descriptions Pin Mnemonic Description
1 PGND Power Ground. 2 SW Connection from Power MOSFETs to Inductor. 3 AGND Analog Ground. 4 FB Feedback from Buck Output. 5 VIN2 LDO Input Voltage. 6 VOUT2 LDO Output Voltage. 7 EN2 Logic 1 to Enable LDO or No Connect for Autosequencing. 8 EN1 Logic 1 to Enable Buck or Initiate Sequencing. This is a dual function pin and the state of EN2 determines which function is operational. 9 PG Power Good. Open-drain output. PG is held low until both output voltages (which includes the external inductor and capacitor sensed by the FB pin) rise above 92% of nominal value. PG is held high until both outputs fall below 85% of nominal value. 10 VIN1 Analog Power Input. EP Exposed Pad. The exposed pad on the bottom of the LFCSP package enhances thermal performance and is electrically connected to ground inside the package. It is recommended that the exposed pad be connected to the ground plane on the circuit board. Rev. A | Page 6 of 32 Document Outline Features Applications General Description Typical Application Circuits Revision History Specifications Recommended Specifications: Capacitors and Inductor Pin Configuration and Function Descriptions Typical Performance Characteristics Buck Output LDO Output Theory of Operation Buck Section Control Scheme PWM Operation PSM Operation Pulse Skipping Threshold Selected Features Short-Circuit Protection Undervoltage Lockout Thermal Protection Soft Start Current Limit Power-Good Pin LDO Section Applications Information Power Sequencing Power-Good Function External Component Selection Selecting the Inductor Output Capacitor Input Capacitor Efficiency Power Switch Conduction Losses Inductor Losses Switching Losses Transition Losses Recommended Buck External Components LDO Capacitor Selection Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties LDO as a Postregulator to Reduce Buck Output Noise Thermal Considerations PCB Layout Considerations Outline Dimensions Ordering Guide
3
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD BE
-00
CONNECTED TO THE GROUND PLANE ON THE CIRCUIT BOARD.
932 07 Figure 3. Pin Configuration
Table 5. Pin Function Descriptions Pin Mnemonic Description
1 PGND Power Ground. 2 SW Connection from Power MOSFETs to Inductor. 3 AGND Analog Ground. 4 FB Feedback from Buck Output. 5 VIN2 LDO Input Voltage. 6 VOUT2 LDO Output Voltage. 7 EN2 Logic 1 to Enable LDO or No Connect for Autosequencing. 8 EN1 Logic 1 to Enable Buck or Initiate Sequencing. This is a dual function pin and the state of EN2 determines which function is operational. 9 PG Power Good. Open-drain output. PG is held low until both output voltages (which includes the external inductor and capacitor sensed by the FB pin) rise above 92% of nominal value. PG is held high until both outputs fall below 85% of nominal value. 10 VIN1 Analog Power Input. EP Exposed Pad. The exposed pad on the bottom of the LFCSP package enhances thermal performance and is electrically connected to ground inside the package. It is recommended that the exposed pad be connected to the ground plane on the circuit board. Rev. A | Page 6 of 32 Document Outline Features Applications General Description Typical Application Circuits Revision History Specifications Recommended Specifications: Capacitors and Inductor Pin Configuration and Function Descriptions Typical Performance Characteristics Buck Output LDO Output Theory of Operation Buck Section Control Scheme PWM Operation PSM Operation Pulse Skipping Threshold Selected Features Short-Circuit Protection Undervoltage Lockout Thermal Protection Soft Start Current Limit Power-Good Pin LDO Section Applications Information Power Sequencing Power-Good Function External Component Selection Selecting the Inductor Output Capacitor Input Capacitor Efficiency Power Switch Conduction Losses Inductor Losses Switching Losses Transition Losses Recommended Buck External Components LDO Capacitor Selection Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties LDO as a Postregulator to Reduce Buck Output Noise Thermal Considerations PCB Layout Considerations Outline Dimensions Ordering Guide