Datasheet ADP2118 (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | 3 A, 1.2 MHz/600 kHz High Efficiency Synchronous Step-Down DC-to-DC Regulator |
| 页数 / 页 | 24 / 3 — Data Sheet. ADP2118. SPECIFICATIONS. Table 1. Parameter. Symbol. Test … |
| 修订版 | E |
| 文件格式/大小 | PDF / 1.1 Mb |
| 文件语言 | 英语 |
Data Sheet. ADP2118. SPECIFICATIONS. Table 1. Parameter. Symbol. Test Conditions/Comments. Min. Typ. Max. Unit
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Data Sheet ADP2118 SPECIFICATIONS
VIN = PVIN = 3.3 V, EN = VIN, SYNC/MODE = high @ TJ = −40°C to +125°C, unless otherwise noted. Typical values are at TJ = 25oC.
Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
VIN AND PVIN VIN Voltage Range VIN 2.3 5.5 V PVIN Voltage Range PVIN 2.3 5.5 V Quiescent Current IVIN No switching, SYNC/MODE = GND 100 150 µA Switching, no load, SYNC/MODE = high 680 900 µA Shutdown Current ISHDN VIN = PVIN = 5.5 V, EN = GND 0.3 3 µA VIN Undervoltage Lockout Threshold UVLO VIN rising 2.2 2.3 V VIN falling 2 2.1 V OUTPUT CHARACTERISTICS Load Regulation1 Io = 0 A to 3 A 0.08 %/A Line Regulation1 Io = 1.5 A 0.05 %/V FB FB Regulation Voltage VFB VIN = 2.3 V to 5.5 V 0.591 0.6 0.609 V FB Bias Current IFB 0.01 0.1 µA SW High-Side On Resistance2 VIN = PVIN = 3.3 V, ISW = 500 mA 75 110 mΩ Low-Side On Resistance2 VIN = PVIN = 3.3 V, ISW = 500 mA 40 60 mΩ SW Peak Current Limit High-side switch, VIN = PVIN = 3.3 V 4 5.2 6.4 A SW Maximum Duty Cycle VIN = PVIN = 5.5 V, full frequency 100 % SW Minimum On Time3 VIN = PVIN = 5.5 V, full frequency 100 ns TRK TRK Input Voltage Range 0 600 mV TRK to FB Offset Voltage TRK = 0 mV to 500 mV −10 +10 mV TRK Input Bias Current 100 nA FREQUENCY Oscillator Frequency FREQ = VIN 1.0 1.2 1.4 MHz FREQ = GND 500 600 700 kHz FREQ Input High Voltage 1.2 V FREQ Input Low Voltage 0.4 V SYNC/MODE Synchronization Range 0.6 1.4 MHz SYNC Minimum Pulse Width 100 ns SYNC Minimum Off Time 100 ns SYNC Input High Voltage 1.2 V SYNC Input Low Voltage 0.4 V INTEGRATED SOFT START Soft Start Time All switching frequency 2048 Clock cycles PGOOD Power Good Range FB rising threshold 105 110 115 % FB rising hysteresis 2.5 % FB falling threshold 85 90 94 % FB falling hysteresis 2.5 % Power Good Deglitch Time From FB to PGOOD 16 Clock cycles PGOOD Leakage Current VPGOOD = 5 V 0.1 1 µA PGOOD Output Low Voltage IPGOOD = 1 mA 140 200 mV Rev. E | Page 3 of 24 Document Outline Features Applications General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance Boundary Conditions ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Functional Block Diagram Theory of Operation Control Scheme PWM Mode Operation PFM Mode Operation Slope Compensation Enable/Shutdown Integrated Soft Start Tracking Oscillator and Synchronization Current Limit and Short-Circuit Protection Overvoltage Protection (OVP) Undervoltage Lockout (UVLO) Thermal Shutdown Power Good Applications Information ADIsimPower™ Design Tool Output Voltage Selection Inductor Selection Output Capacitor Selection Input Capacitor Selection Voltage Tracking Typical Application Circuits Outline Dimensions Ordering Guide
Data Sheet ADP2118 SPECIFICATIONS
VIN = PVIN = 3.3 V, EN = VIN, SYNC/MODE = high @ TJ = −40°C to +125°C, unless otherwise noted. Typical values are at TJ = 25oC.
Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
VIN AND PVIN VIN Voltage Range VIN 2.3 5.5 V PVIN Voltage Range PVIN 2.3 5.5 V Quiescent Current IVIN No switching, SYNC/MODE = GND 100 150 µA Switching, no load, SYNC/MODE = high 680 900 µA Shutdown Current ISHDN VIN = PVIN = 5.5 V, EN = GND 0.3 3 µA VIN Undervoltage Lockout Threshold UVLO VIN rising 2.2 2.3 V VIN falling 2 2.1 V OUTPUT CHARACTERISTICS Load Regulation1 Io = 0 A to 3 A 0.08 %/A Line Regulation1 Io = 1.5 A 0.05 %/V FB FB Regulation Voltage VFB VIN = 2.3 V to 5.5 V 0.591 0.6 0.609 V FB Bias Current IFB 0.01 0.1 µA SW High-Side On Resistance2 VIN = PVIN = 3.3 V, ISW = 500 mA 75 110 mΩ Low-Side On Resistance2 VIN = PVIN = 3.3 V, ISW = 500 mA 40 60 mΩ SW Peak Current Limit High-side switch, VIN = PVIN = 3.3 V 4 5.2 6.4 A SW Maximum Duty Cycle VIN = PVIN = 5.5 V, full frequency 100 % SW Minimum On Time3 VIN = PVIN = 5.5 V, full frequency 100 ns TRK TRK Input Voltage Range 0 600 mV TRK to FB Offset Voltage TRK = 0 mV to 500 mV −10 +10 mV TRK Input Bias Current 100 nA FREQUENCY Oscillator Frequency FREQ = VIN 1.0 1.2 1.4 MHz FREQ = GND 500 600 700 kHz FREQ Input High Voltage 1.2 V FREQ Input Low Voltage 0.4 V SYNC/MODE Synchronization Range 0.6 1.4 MHz SYNC Minimum Pulse Width 100 ns SYNC Minimum Off Time 100 ns SYNC Input High Voltage 1.2 V SYNC Input Low Voltage 0.4 V INTEGRATED SOFT START Soft Start Time All switching frequency 2048 Clock cycles PGOOD Power Good Range FB rising threshold 105 110 115 % FB rising hysteresis 2.5 % FB falling threshold 85 90 94 % FB falling hysteresis 2.5 % Power Good Deglitch Time From FB to PGOOD 16 Clock cycles PGOOD Leakage Current VPGOOD = 5 V 0.1 1 µA PGOOD Output Low Voltage IPGOOD = 1 mA 140 200 mV Rev. E | Page 3 of 24 Document Outline Features Applications General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance Boundary Conditions ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Functional Block Diagram Theory of Operation Control Scheme PWM Mode Operation PFM Mode Operation Slope Compensation Enable/Shutdown Integrated Soft Start Tracking Oscillator and Synchronization Current Limit and Short-Circuit Protection Overvoltage Protection (OVP) Undervoltage Lockout (UVLO) Thermal Shutdown Power Good Applications Information ADIsimPower™ Design Tool Output Voltage Selection Inductor Selection Output Capacitor Selection Input Capacitor Selection Voltage Tracking Typical Application Circuits Outline Dimensions Ordering Guide