Datasheet LTC3409A (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | 600mA Low VIN Buck Regulator in 3mm × 3mm DFN |
| 页数 / 页 | 16 / 3 — The. ELECTRICAL CHARACTERISTICS. denotes specifi cations which apply over … |
| 文件格式/大小 | PDF / 321 Kb |
| 文件语言 | 英语 |
The. ELECTRICAL CHARACTERISTICS. denotes specifi cations which apply over the full operating
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LTC3409A
The ELECTRICAL CHARACTERISTICS
●
denotes specifi cations which apply over the full operating temperature range, otherwise specifi cations are TA = 25°C. VIN = 2.2V unless otherwise specifi ed. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VSYNCTH SYNC Threshold l 0.3 0.65 1.1 V ISYNC SYNC Leakage Current VSYNC = 0V or = 2.2V 0.01 1 μA IS Input DC Bias Current (Note 5) Active Mode VOUT = 90%, ILOAD = 0A 350 475 μA Sleep Mode VOUT = 103%, ILOAD = 0A 65 120 μA Shutdown VRUN = 0V, VIN = 5.5V 0.1 1 μA fOSC Nominal Oscillator Frequency SYNC = GND l 0.9 1.7 2.2 MHz SYNC = VIN l 1.8 2.6 3.2 MHz SYNC TH SYNC Threshold When SYNC Input is Toggling (Note 7) 0.63 V SYNC fMIN Minimum SYNC Pin Frequency 1 MHz SYNC fMAX Maximum SYNC Pin Frequency 3 MHz SYNC PW Minimum SYNC Pulse Width 100 ns tSS Soft-Start Period RUN↑ 1 ms SYNC tO SYNC Timeout Delay from Removal of EXT CLK Until Fixed 30 μs Frequency Operation Begins (Note 7) RPFET RDS(ON) of P-channel FET ISW = 100mA, Wafer Level 0.33 Ω ISW = 100mA, DD Package 0.35 Ω RNFET RDS(ON) of N-channel FET ISW = 100mA, Wafer Level 0.22 Ω ISW = 100mA, DD Package 0.25 Ω ILSW SW Leakage VRUN = 0V, VSW = 0V or 5V, VIN = 5V ±0.1 ±3 μA
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings This IC includes overtemperature protection that is intended to protect the may cause permanent damage to the device. Exposure to any Absolute device during momentary overload conditions. Overtemperature protection Maximum Rating condition for extended periods may affect device becomes active at a junction temperature greater than the maximum reliability and lifetime. operating junction temperature. Continuous operation above the specifi ed
Note 2:
The LTC3409AE is guaranteed to meet performance specifi cations maximum operating junction temperature may impair device reliability. from 0°C to 85°C. Specifi cations over the –40°C to 85°C operating
Note 4:
The LTC3409A is tested in a proprietary test mode that connects temperature range are assured by design, characterization and correlation VFB to the output of the error amplifi er. with statistical process controls. The LTC3409AI is guaranteed to meet
Note 5:
Dynamic supply current is higher due to the gate charge being specifi ed performance over the full –40°C to 85°C operating temperature delivered at the switching frequency. range.
Note 6:
ΔVOVL is the amount VFB must exceed the regulated feedback
Note 3:
TJ is calculated from the ambient temperature TA and power voltage. dissipation PD according to the following formula:
Note 7:
Determined by design, not production tested. LTC3409A: TJ = TA + (PD)(43°C/W)
Note 8:
Guaranteed by measurement at the wafer level and design, characterization and correlation with statistical process controls. 3409af 3
The ELECTRICAL CHARACTERISTICS
●
denotes specifi cations which apply over the full operating temperature range, otherwise specifi cations are TA = 25°C. VIN = 2.2V unless otherwise specifi ed. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VSYNCTH SYNC Threshold l 0.3 0.65 1.1 V ISYNC SYNC Leakage Current VSYNC = 0V or = 2.2V 0.01 1 μA IS Input DC Bias Current (Note 5) Active Mode VOUT = 90%, ILOAD = 0A 350 475 μA Sleep Mode VOUT = 103%, ILOAD = 0A 65 120 μA Shutdown VRUN = 0V, VIN = 5.5V 0.1 1 μA fOSC Nominal Oscillator Frequency SYNC = GND l 0.9 1.7 2.2 MHz SYNC = VIN l 1.8 2.6 3.2 MHz SYNC TH SYNC Threshold When SYNC Input is Toggling (Note 7) 0.63 V SYNC fMIN Minimum SYNC Pin Frequency 1 MHz SYNC fMAX Maximum SYNC Pin Frequency 3 MHz SYNC PW Minimum SYNC Pulse Width 100 ns tSS Soft-Start Period RUN↑ 1 ms SYNC tO SYNC Timeout Delay from Removal of EXT CLK Until Fixed 30 μs Frequency Operation Begins (Note 7) RPFET RDS(ON) of P-channel FET ISW = 100mA, Wafer Level 0.33 Ω ISW = 100mA, DD Package 0.35 Ω RNFET RDS(ON) of N-channel FET ISW = 100mA, Wafer Level 0.22 Ω ISW = 100mA, DD Package 0.25 Ω ILSW SW Leakage VRUN = 0V, VSW = 0V or 5V, VIN = 5V ±0.1 ±3 μA
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings This IC includes overtemperature protection that is intended to protect the may cause permanent damage to the device. Exposure to any Absolute device during momentary overload conditions. Overtemperature protection Maximum Rating condition for extended periods may affect device becomes active at a junction temperature greater than the maximum reliability and lifetime. operating junction temperature. Continuous operation above the specifi ed
Note 2:
The LTC3409AE is guaranteed to meet performance specifi cations maximum operating junction temperature may impair device reliability. from 0°C to 85°C. Specifi cations over the –40°C to 85°C operating
Note 4:
The LTC3409A is tested in a proprietary test mode that connects temperature range are assured by design, characterization and correlation VFB to the output of the error amplifi er. with statistical process controls. The LTC3409AI is guaranteed to meet
Note 5:
Dynamic supply current is higher due to the gate charge being specifi ed performance over the full –40°C to 85°C operating temperature delivered at the switching frequency. range.
Note 6:
ΔVOVL is the amount VFB must exceed the regulated feedback
Note 3:
TJ is calculated from the ambient temperature TA and power voltage. dissipation PD according to the following formula:
Note 7:
Determined by design, not production tested. LTC3409A: TJ = TA + (PD)(43°C/W)
Note 8:
Guaranteed by measurement at the wafer level and design, characterization and correlation with statistical process controls. 3409af 3