Datasheet LTC3569 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | Triple Buck Regulator with 1.2A and Two 600mA Outputs and Individual Programmable References |
| 页数 / 页 | 26 / 8 — pin FuncTions EN1:. PGND2:. EN2:. PGND3:. EN3:. PGOOD:. FB1:. PVIN1:. … |
| 文件格式/大小 | PDF / 399 Kb |
| 文件语言 | 英语 |
pin FuncTions EN1:. PGND2:. EN2:. PGND3:. EN3:. PGOOD:. FB1:. PVIN1:. FB2:. PVIN2:. FB3:. PVIN3:. GND (Exposed Pad):. RT:. MODE:. SGND:. IN:. SW1:. SW2:
该数据表的模型线
文件文字版本
LTC3569
pin FuncTions EN1:
Enable Pin for Buck 1. Toggle up to 15 times to
PGND2:
Main Power Ground Pin for Buck 2. Connect to program reference feedback level from 800mV down to the (–) terminal of the output capacitor for Buck2, and (–) 425mV. terminal of CIN2. Decoupling capacitors should be summed
EN2:
Enable Pin for Buck 2. Toggle up to 15 times to where power supply pins are shared. program reference feedback level from 800mV down to
PGND3:
Main Power Ground Pin for Buck 3. Connect to 425mV. the (–) terminal of the output capacitor for Buck3, and (–)
EN3:
Enable Pin for Buck 3. Toggle up to 15 times to terminal of CIN3. Decoupling capacitors should be summed program reference feedback level from 800mV down to where power supply pins are shared. 425mV.
PGOOD:
The Power Good Pin. This open-drain output is
FB1:
Receives the feedback voltage from the external released when an enabled output has risen to within 8% of resistive divider across the output of Buck 1. Nominal the regulation voltage. When multiple outputs are enabled, voltage for this pin is programmed with the EN1 pin from PGOOD is the logical AND of each internal PGOOD. 800mV down to 425mV.
PVIN1:
Main Supply Pin for Buck 1. Decouple to PGND1
FB2:
Receives the feedback voltage from the external with a low ESR 4.7µF capacitor, CIN1. Decoupling ca- resistive divider across the output of Buck 2. Nominal pacitors should be summed where power supply pins voltage for this pin is programmed with the EN2 pin from are shared. 800mV down to 425mV. When pulled to SVIN, Buck 2 is
PVIN2:
Main Supply Pin for Buck 2. Decouple to PGND2 put into slave mode, following Buck 1. with a low ESR 4.7µF capacitor, CIN2. Decoupling ca-
FB3:
Receives the feedback voltage from the external pacitors should be summed where power supply pins resistive divider across the output of Buck 3. Nominal are shared. voltage for this pin is programmed with the EN3 pin from
PVIN3:
Main Supply Pin for Buck 3. Decouple to PGND3 800mV down to 425mV. When pulled to SVIN, Buck 3 is with a low ESR 4.7µF capacitor, CIN3. Decoupling capacitors put into slave mode, following Buck 2. should be summed where power supply pins are shared.
GND (Exposed Pad):
The exposed pad must be connected For 16-lead plastic TSSOP FE package, PVIN1 and PVIN3 to PCB ground for rated thermal performance and for share pin 8. electrical connection in the TSSOP package.
RT:
Timing Resistor Pin. The free-running oscillator
MODE:
Combination Mode Selection and Oscillator Syn- frequency is programmed by connecting a resistor from chronization Pin. This pin controls the operating mode this pin to ground. Tie to SVIN to get a fixed 2.25MHz of the device. When tied to SV operating frequency. IN, Burst Mode operation is selected. When tied to SGND, pulse-skipping mode is
SGND:
Main Ground Pin. Decouple to SVIN. selected. The internal clock frequency synchronizes to an
SV
external oscillator applied to this pin. When synchronizing
IN:
Main Supply Pin. Decouple to SGND with a low ESR 1µF capacitor. to an external clock, drive this pin with a logic-level signal with high and low pulse widths of at least 100ns. When
SW1:
Buck 1 Switch. Connect to the Inductor for Buck 1. synchronizing to an external clock, pulse-skipping mode This pin swings from PVIN1 to PGND1. is automatically selected.
SW2:
Buck 2 Switch. Connect to the Inductor for Buck 2.
PGND1:
Main Power Ground Pin for Buck 1. Connect to This pin swings from PVIN2 to PGND2. the (–) terminal of the output capacitor for Buck1, and (–)
SW3:
Buck 3 Switch. Connect to the Inductor for Buck 3. terminal of CIN1. Decoupling capacitors should be summed This pin swings from PV where power supply pins are shared. IN3 to PGND3. 3569fe 8 For more information www.linear.com/LTC3569 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts
pin FuncTions EN1:
Enable Pin for Buck 1. Toggle up to 15 times to
PGND2:
Main Power Ground Pin for Buck 2. Connect to program reference feedback level from 800mV down to the (–) terminal of the output capacitor for Buck2, and (–) 425mV. terminal of CIN2. Decoupling capacitors should be summed
EN2:
Enable Pin for Buck 2. Toggle up to 15 times to where power supply pins are shared. program reference feedback level from 800mV down to
PGND3:
Main Power Ground Pin for Buck 3. Connect to 425mV. the (–) terminal of the output capacitor for Buck3, and (–)
EN3:
Enable Pin for Buck 3. Toggle up to 15 times to terminal of CIN3. Decoupling capacitors should be summed program reference feedback level from 800mV down to where power supply pins are shared. 425mV.
PGOOD:
The Power Good Pin. This open-drain output is
FB1:
Receives the feedback voltage from the external released when an enabled output has risen to within 8% of resistive divider across the output of Buck 1. Nominal the regulation voltage. When multiple outputs are enabled, voltage for this pin is programmed with the EN1 pin from PGOOD is the logical AND of each internal PGOOD. 800mV down to 425mV.
PVIN1:
Main Supply Pin for Buck 1. Decouple to PGND1
FB2:
Receives the feedback voltage from the external with a low ESR 4.7µF capacitor, CIN1. Decoupling ca- resistive divider across the output of Buck 2. Nominal pacitors should be summed where power supply pins voltage for this pin is programmed with the EN2 pin from are shared. 800mV down to 425mV. When pulled to SVIN, Buck 2 is
PVIN2:
Main Supply Pin for Buck 2. Decouple to PGND2 put into slave mode, following Buck 1. with a low ESR 4.7µF capacitor, CIN2. Decoupling ca-
FB3:
Receives the feedback voltage from the external pacitors should be summed where power supply pins resistive divider across the output of Buck 3. Nominal are shared. voltage for this pin is programmed with the EN3 pin from
PVIN3:
Main Supply Pin for Buck 3. Decouple to PGND3 800mV down to 425mV. When pulled to SVIN, Buck 3 is with a low ESR 4.7µF capacitor, CIN3. Decoupling capacitors put into slave mode, following Buck 2. should be summed where power supply pins are shared.
GND (Exposed Pad):
The exposed pad must be connected For 16-lead plastic TSSOP FE package, PVIN1 and PVIN3 to PCB ground for rated thermal performance and for share pin 8. electrical connection in the TSSOP package.
RT:
Timing Resistor Pin. The free-running oscillator
MODE:
Combination Mode Selection and Oscillator Syn- frequency is programmed by connecting a resistor from chronization Pin. This pin controls the operating mode this pin to ground. Tie to SVIN to get a fixed 2.25MHz of the device. When tied to SV operating frequency. IN, Burst Mode operation is selected. When tied to SGND, pulse-skipping mode is
SGND:
Main Ground Pin. Decouple to SVIN. selected. The internal clock frequency synchronizes to an
SV
external oscillator applied to this pin. When synchronizing
IN:
Main Supply Pin. Decouple to SGND with a low ESR 1µF capacitor. to an external clock, drive this pin with a logic-level signal with high and low pulse widths of at least 100ns. When
SW1:
Buck 1 Switch. Connect to the Inductor for Buck 1. synchronizing to an external clock, pulse-skipping mode This pin swings from PVIN1 to PGND1. is automatically selected.
SW2:
Buck 2 Switch. Connect to the Inductor for Buck 2.
PGND1:
Main Power Ground Pin for Buck 1. Connect to This pin swings from PVIN2 to PGND2. the (–) terminal of the output capacitor for Buck1, and (–)
SW3:
Buck 3 Switch. Connect to the Inductor for Buck 3. terminal of CIN1. Decoupling capacitors should be summed This pin swings from PV where power supply pins are shared. IN3 to PGND3. 3569fe 8 For more information www.linear.com/LTC3569 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts