Datasheet LTC3568 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 1.8A, 4MHz, Synchronous Step-Down DC/DC Converter |
| 页数 / 页 | 18 / 6 — SHDN/RT (Pin 1):. PGND (Pin 5):. IN (Pin 6):. SYNC/MODE (Pin 2):. … |
| 文件格式/大小 | PDF / 313 Kb |
| 文件语言 | 英语 |
SHDN/RT (Pin 1):. PGND (Pin 5):. IN (Pin 6):. SYNC/MODE (Pin 2):. IN (Pin 7):. PGOOD (Pin 8):. FB (Pin 9):. SGND (Pin 3):. TH (Pin 10):
该数据表的模型线
文件文字版本
LTC3568 pin FuncTions
SHDN/RT (Pin 1):
Combination Shutdown and Timing
PGND (Pin 5):
Main Power Ground Pin. Connect to the Resistor Pin. The oscillator frequency is programmed by (–) terminal of COUT, and (–) terminal of CIN. connecting a resistor from this pin to ground. Forcing
PV
this pin to SV
IN (Pin 6):
Main Supply Pin. Must be closely decoupled IN causes the device to be shut down. In to PGND. shutdown all functions are disabled.
SV SYNC/MODE (Pin 2):
Combination Mode Selection and
IN (Pin 7):
The Signal Power Pin. All active circuitry is powered from this pin. Must be closely decoupled to Oscillator Synchronization Pin. This pin controls the op- SGND. SV eration of the device. When tied to SV IN must be greater than or equal to PVIN. IN or SGND, Burst Mode operation or pulse skipping mode is selected,
PGOOD (Pin 8):
The Power Good Pin. This common drain respectively. If this pin is held at half of SVIN, the forced logic output is pulled to SGND when the output voltage is continuous mode is selected. The oscillation frequency not within ±7.5% of regulation. can be syncronized to an external oscillator applied to
V
this pin. When synchronized to an external clock pulse
FB (Pin 9):
Receives the feedback voltage from the ex- ternal resistive divider across the output. Nominal voltage skip mode is selected. for this pin is 0.8V.
SGND (Pin 3):
The Signal Ground Pin. Al smal signal
I
components and compensation components should be con-
TH (Pin 10):
Error Amplifier Compensation Point. The current comparator threshold increases with this control nected to this ground (see Board Layout Considerations). voltage. Nominal voltage range for this pin is 0V to 1.5V.
SW (Pin 4):
The Switch Node Connection to the Inductor.
GND (Exposed Pad Pin 11):
Thermal Ground. Con- This pin swings from PVIN to PGND. nect to SGND and solder to the PCB for rated thermal performance. block DiagraM SVIN SGND ITH PVIN 7 3 10 6 0.8V VOLTAGE PMOS CURRENT REFERENCE COMPARATOR ITH LIMIT + + BCLAMP – – VFB 9 – ERROR AMPLIFIER + VB BURST 0.74V + COMPARATOR HYSTERESIS = 80mV SLOPE 4 SW – COMPENSATION OSCILLATOR + + LOGIC 0.86V – – NMOS PGOOD 8 COMPARATOR – + 5 PGND REVERSE COMPARATOR 1 2 SHDN/RT SYNC/MODE 3568 BD 3568fa Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
SHDN/RT (Pin 1):
Combination Shutdown and Timing
PGND (Pin 5):
Main Power Ground Pin. Connect to the Resistor Pin. The oscillator frequency is programmed by (–) terminal of COUT, and (–) terminal of CIN. connecting a resistor from this pin to ground. Forcing
PV
this pin to SV
IN (Pin 6):
Main Supply Pin. Must be closely decoupled IN causes the device to be shut down. In to PGND. shutdown all functions are disabled.
SV SYNC/MODE (Pin 2):
Combination Mode Selection and
IN (Pin 7):
The Signal Power Pin. All active circuitry is powered from this pin. Must be closely decoupled to Oscillator Synchronization Pin. This pin controls the op- SGND. SV eration of the device. When tied to SV IN must be greater than or equal to PVIN. IN or SGND, Burst Mode operation or pulse skipping mode is selected,
PGOOD (Pin 8):
The Power Good Pin. This common drain respectively. If this pin is held at half of SVIN, the forced logic output is pulled to SGND when the output voltage is continuous mode is selected. The oscillation frequency not within ±7.5% of regulation. can be syncronized to an external oscillator applied to
V
this pin. When synchronized to an external clock pulse
FB (Pin 9):
Receives the feedback voltage from the ex- ternal resistive divider across the output. Nominal voltage skip mode is selected. for this pin is 0.8V.
SGND (Pin 3):
The Signal Ground Pin. Al smal signal
I
components and compensation components should be con-
TH (Pin 10):
Error Amplifier Compensation Point. The current comparator threshold increases with this control nected to this ground (see Board Layout Considerations). voltage. Nominal voltage range for this pin is 0V to 1.5V.
SW (Pin 4):
The Switch Node Connection to the Inductor.
GND (Exposed Pad Pin 11):
Thermal Ground. Con- This pin swings from PVIN to PGND. nect to SGND and solder to the PCB for rated thermal performance. block DiagraM SVIN SGND ITH PVIN 7 3 10 6 0.8V VOLTAGE PMOS CURRENT REFERENCE COMPARATOR ITH LIMIT + + BCLAMP – – VFB 9 – ERROR AMPLIFIER + VB BURST 0.74V + COMPARATOR HYSTERESIS = 80mV SLOPE 4 SW – COMPENSATION OSCILLATOR + + LOGIC 0.86V – – NMOS PGOOD 8 COMPARATOR – + 5 PGND REVERSE COMPARATOR 1 2 SHDN/RT SYNC/MODE 3568 BD 3568fa Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts