Datasheet LTC3602 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 2.5A, 10V, Monolithic Synchronous Step-Down Regulator |
| 页数 / 页 | 20 / 6 — PIN FUNCTIONS FE/UF Package. SYNC/MODE (Pin 1/Pin 4):. PGOOD (Pin 2/Pin … |
| 文件格式/大小 | PDF / 230 Kb |
| 文件语言 | 英语 |
PIN FUNCTIONS FE/UF Package. SYNC/MODE (Pin 1/Pin 4):. PGOOD (Pin 2/Pin 5):. PGND (Pins 8, 9, 10/Pins 12, 13, 14, 15):
该数据表的模型线
文件文字版本
LTC3602
PIN FUNCTIONS FE/UF Package SYNC/MODE (Pin 1/Pin 4):
Mode Select and External be programmed by connecting a capacitor between this Clock Synchronization Input. pin and ground. Leave this pin fl oating to use the internal 1ms soft-start clamp. Do not tie this pin to INTV
PGOOD (Pin 2/Pin 5):
Power Good Output. Open-drain CC or to PV logic output that is pulled to ground when the output volt- IN. age is not within ±10% of regulation point.
PGND (Pins 8, 9, 10/Pins 12, 13, 14, 15):
Power Ground.
RT (Pin 3/Pin 6):
Frequency Set Pin.
SW (Pins 11, 12, 13/Pins 16, 17, 18, 19):
Switch Node
ITH (Pin 4/Pin 7):
Error Amplifi er Compensation Point. Connection to the Inductor.
VFB (Pin 5/Pin 8):
Feedback Pin.
BOOST (Pin 14/Pin 20):
Bootstrapped Supply to the Top
SGND (Pin 17/Pin 9, Pin 21):
Signal Ground. Side Floating Gate Driver.
RUN (Pin 6/Pin 10):
Run Control Input. This pin may be
PVIN (Pin 15/Pins 1,2):
Power Input Supply. Decouple tied to PVIN to enable the chip. this pin with a capacitor to PGND
TRACK/SS (Pin 7/Pin 11):
Tracking Input for the Controller
INTVCC (Pin 16/Pin 3):
Output of Internal 5V LDO. or Optional External Soft-Start Input. This pin allows the
Exposed Pad (Pin 17/Pin 21):
SGND. Exposed pad is start-up of VOUT to “track” the external voltage at this pin signal ground and must be soldered to the PCB. using an external resistor divider. An external soft-start can
BLOCK DIAGRAM
I BOOST TH INTVCC PVIN 1μA LDO 0.6V VOLTAGE REFERENCE SLOPE COMPENSATION RECOVERY TRACK/SS 1ms SOFT-START BCLAMP + ERROR + AMPLIFIER BURST + COMPARATOR MAIN – + + I-COMPARATOR VFB – SYNC/MODE – SW + – 0.54V + SW SLOPE COMPENSATION OSILLATOR – OVER-CURRENT SW COMPARATOR + + 0.66V LOGIC – PGND – REVERSE PGND PGOOD COMPARATOR + PGND – R RUN T SYNC/MODE 3602 BD 3602fb 6
PIN FUNCTIONS FE/UF Package SYNC/MODE (Pin 1/Pin 4):
Mode Select and External be programmed by connecting a capacitor between this Clock Synchronization Input. pin and ground. Leave this pin fl oating to use the internal 1ms soft-start clamp. Do not tie this pin to INTV
PGOOD (Pin 2/Pin 5):
Power Good Output. Open-drain CC or to PV logic output that is pulled to ground when the output volt- IN. age is not within ±10% of regulation point.
PGND (Pins 8, 9, 10/Pins 12, 13, 14, 15):
Power Ground.
RT (Pin 3/Pin 6):
Frequency Set Pin.
SW (Pins 11, 12, 13/Pins 16, 17, 18, 19):
Switch Node
ITH (Pin 4/Pin 7):
Error Amplifi er Compensation Point. Connection to the Inductor.
VFB (Pin 5/Pin 8):
Feedback Pin.
BOOST (Pin 14/Pin 20):
Bootstrapped Supply to the Top
SGND (Pin 17/Pin 9, Pin 21):
Signal Ground. Side Floating Gate Driver.
RUN (Pin 6/Pin 10):
Run Control Input. This pin may be
PVIN (Pin 15/Pins 1,2):
Power Input Supply. Decouple tied to PVIN to enable the chip. this pin with a capacitor to PGND
TRACK/SS (Pin 7/Pin 11):
Tracking Input for the Controller
INTVCC (Pin 16/Pin 3):
Output of Internal 5V LDO. or Optional External Soft-Start Input. This pin allows the
Exposed Pad (Pin 17/Pin 21):
SGND. Exposed pad is start-up of VOUT to “track” the external voltage at this pin signal ground and must be soldered to the PCB. using an external resistor divider. An external soft-start can
BLOCK DIAGRAM
I BOOST TH INTVCC PVIN 1μA LDO 0.6V VOLTAGE REFERENCE SLOPE COMPENSATION RECOVERY TRACK/SS 1ms SOFT-START BCLAMP + ERROR + AMPLIFIER BURST + COMPARATOR MAIN – + + I-COMPARATOR VFB – SYNC/MODE – SW + – 0.54V + SW SLOPE COMPENSATION OSILLATOR – OVER-CURRENT SW COMPARATOR + + 0.66V LOGIC – PGND – REVERSE PGND PGOOD COMPARATOR + PGND – R RUN T SYNC/MODE 3602 BD 3602fb 6