Datasheet LT3501 (Analog Devices) - 10

LT3501
block DiagraM
RT/SYNC ONE CHANNEL VIN R3 V C IN1 CLK1 INTERNAL OSCILLATOR REGULATOR AND AND AGC CLK2 REFERENCE DROPOUT BST ENHANCEMENT 3µA 7µA SLOPE C3 COMPENSATION – S PRE Σ Q DRIVER SHDN + + R CIRCUITRY SW + – SHUTDOWN L1 D 1.28V COMPARATOR IND POR + UNDERVOLTAGE D TSD – VOUT + 0.8V C + R1 LOWEST – FB VOLTAGE V R2 S C CLAMP R Q POWER GOOD 3.25mA COMPARATOR PGOOD – – + + + SS CLAMP + SOFT-START 80mV 0.72V GND RESET COMPARATOR 3501 BD SS VC C
Figure 1. Block Diagram (One of Two Switching Regulators Shown)
The LT3501 is dual-channel, constant-frequency, current When the SHDN pin is opened or driven above 1.28V, mode buck converter with internal 3A switches. Each the internal bias circuits turn on generating an internal channel is identical with a common shutdown pin, internal regulated voltage, 0.8VFB, 0.975V RT/SYNC references, regulator, oscillator, undervoltage detect, thermal shutdown and a POR signal which sets the soft-start latch. and power-on reset. As the RT/SYNC pin reaches its 0.975V regulation point, If the SHDN pin is taken below its 1.28V threshold the the internal oscillator will start generating two clock sig- LT3501 will be placed in a low quiescent current mode. nals 180° out of phase for each regulator at a frequency In this mode the LT3501 typically draws 9µA from VIN1 determined by the resistor from the RT/SYNC pin to ground. and <1µA from VIN2. In shutdown mode the PG is active Alternatively, if a synchronization signal is detected by the with a typical sink capability of 50µA for VIN1 voltage LT3501 at the RT/SYNC pin, clock signals 180° out of phase greater than 2V. 3501fd 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts