Datasheet LTC3548-1 (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | Dual Synchronous, Fixed Output 2.25MHz Step-Down DC/DC Regulator |
| 页数 / 页 | 16 / 3 — ELECTRICAL CHARACTERISTICS The. denotes the specifi cations which apply … |
| 文件格式/大小 | PDF / 332 Kb |
| 文件语言 | 英语 |
ELECTRICAL CHARACTERISTICS The. denotes the specifi cations which apply over the full operating
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LTC3548-1
ELECTRICAL CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 3.6V, unless otherwise specifi ed. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Operating Voltage Range ● 2.5 5.5 V VOUT1 Output Voltage 0°C ≤ TA ≤ 85°C (Note 3) 1.764 1.8 1.836 V –40°C ≤ TA ≤ 85°C (Note 3) ● 1.755 1.8 1.836 V VOUT2 Output Voltage 0°C ≤ TA ≤ 85°C (Note 3) 1.544 1.575 1.607 V –40°C ≤ TA ≤ 85°C (Note 3) ● 1.536 1.575 1.607 V ΔVLINE REG Reference Voltage Line Regulation VIN = 2.5V to 5.5V (Note 3) 0.3 0.5 %/V ΔVLOAD REG Output Voltage Load Regulation (Note 3) 0.5 % IS Input DC Supply Current (Note 4) Active Mode VOUT1 = 1.5V, VOUT2 = 1.3V 700 950 μA Sleep Mode VOUT1 = 1.9V, VOUT2 = 1.65V 40 60 μA Shutdown RUN = 0V, VIN = 5.5V 0.1 1 μA fOSC Oscillator Frequency VOUT1 = 1.8V, VOUT2 = 1.575V ● 1.8 2.25 2.7 MHz ILIM Peak Switch Current Limit Channel 1 VIN = 3V, Duty Cycle <35% 0.95 1.2 1.6 A Peak Switch Current Limit Channel 2 VIN = 3V, Duty Cycle <35% 0.6 0.7 0.9 A RDS(ON) Top Switch On-Resistance (Note 6) 0.35 0.45 Ω Bottom Switch On-Resistance (Note 6) 0.30 0.45 Ω ISW(LKG) Switch Leakage Current VIN = 5V, VRUN = 0V, VOUT1 = VOUT2 = 0 0.01 1 μA VRUN RUN Threshold ● 0.3 1 1.5 V IRUN RUN Leakage Current ● 0.01 1 μA VMODE Mode Threshold Low 0 0.5 V Mode Threshold High VIN – 0.5 VIN V
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 3:
The LTC3548-1 is tested in a proprietary test mode that connects may cause permanent damage to the device. Exposure to any Absolute the output of the error amplifi er to an outside servo-loop. Maximum Rating condition for extended periods may affect device
Note 4:
Dynamic supply current is higher due to the internal gate charge reliability and lifetime. being delivered at the switching frequency.
Note 2:
The LTC3548-1 is guaranteed to meet specifi ed performance from
Note 5:
TJ is calculated from the ambient TA and power dissipation PD 0°C to 85°C. Specifi cations over the – 40°C to 85°C operating temperature according to the following formula: TJ = TA + (PD • θJA). range are assured by design, characterization and correlation with
Note 6:
The DFN switch on-resistance is guaranteed by correlation to statistical process controls. wafer level measurements.
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specifi ed. Burst Mode Operation Load Step Load Step
VOUT2 SW 200mV/DIV 5V/DIV VOUT1 200mV/DIV IL I 200mA/DIV L IL 500mA/DIV 200mA/DIV ILOAD ILOAD 40mA TO V 80mA TO OUT1 400mA 20mV/DIV 800mA 200mA/DIV 500mA/DIV 3548-1 G01 3548-1 G03 V V 20μs/DIV IN = 3.6V 2μs/DIV 3548-1 G02 IN = 3.6V VIN = 3.6V 20μs/DIV V V OUT1 = 1.8V OUT2 = 1.575V VOUT1 = 1.8V I I LOAD = 60mA LOAD = 40mA TO 400mA ILOAD = 80mA TO 800mA CHANNEL 1; CIRCUIT OF FIGURE 3 CHANNEL 2; CIRCUIT OF FIGURE 3 CHANNEL 1; CIRCUIT OF FIGURE 3 35481fc 3
ELECTRICAL CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 3.6V, unless otherwise specifi ed. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Operating Voltage Range ● 2.5 5.5 V VOUT1 Output Voltage 0°C ≤ TA ≤ 85°C (Note 3) 1.764 1.8 1.836 V –40°C ≤ TA ≤ 85°C (Note 3) ● 1.755 1.8 1.836 V VOUT2 Output Voltage 0°C ≤ TA ≤ 85°C (Note 3) 1.544 1.575 1.607 V –40°C ≤ TA ≤ 85°C (Note 3) ● 1.536 1.575 1.607 V ΔVLINE REG Reference Voltage Line Regulation VIN = 2.5V to 5.5V (Note 3) 0.3 0.5 %/V ΔVLOAD REG Output Voltage Load Regulation (Note 3) 0.5 % IS Input DC Supply Current (Note 4) Active Mode VOUT1 = 1.5V, VOUT2 = 1.3V 700 950 μA Sleep Mode VOUT1 = 1.9V, VOUT2 = 1.65V 40 60 μA Shutdown RUN = 0V, VIN = 5.5V 0.1 1 μA fOSC Oscillator Frequency VOUT1 = 1.8V, VOUT2 = 1.575V ● 1.8 2.25 2.7 MHz ILIM Peak Switch Current Limit Channel 1 VIN = 3V, Duty Cycle <35% 0.95 1.2 1.6 A Peak Switch Current Limit Channel 2 VIN = 3V, Duty Cycle <35% 0.6 0.7 0.9 A RDS(ON) Top Switch On-Resistance (Note 6) 0.35 0.45 Ω Bottom Switch On-Resistance (Note 6) 0.30 0.45 Ω ISW(LKG) Switch Leakage Current VIN = 5V, VRUN = 0V, VOUT1 = VOUT2 = 0 0.01 1 μA VRUN RUN Threshold ● 0.3 1 1.5 V IRUN RUN Leakage Current ● 0.01 1 μA VMODE Mode Threshold Low 0 0.5 V Mode Threshold High VIN – 0.5 VIN V
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 3:
The LTC3548-1 is tested in a proprietary test mode that connects may cause permanent damage to the device. Exposure to any Absolute the output of the error amplifi er to an outside servo-loop. Maximum Rating condition for extended periods may affect device
Note 4:
Dynamic supply current is higher due to the internal gate charge reliability and lifetime. being delivered at the switching frequency.
Note 2:
The LTC3548-1 is guaranteed to meet specifi ed performance from
Note 5:
TJ is calculated from the ambient TA and power dissipation PD 0°C to 85°C. Specifi cations over the – 40°C to 85°C operating temperature according to the following formula: TJ = TA + (PD • θJA). range are assured by design, characterization and correlation with
Note 6:
The DFN switch on-resistance is guaranteed by correlation to statistical process controls. wafer level measurements.
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specifi ed. Burst Mode Operation Load Step Load Step
VOUT2 SW 200mV/DIV 5V/DIV VOUT1 200mV/DIV IL I 200mA/DIV L IL 500mA/DIV 200mA/DIV ILOAD ILOAD 40mA TO V 80mA TO OUT1 400mA 20mV/DIV 800mA 200mA/DIV 500mA/DIV 3548-1 G01 3548-1 G03 V V 20μs/DIV IN = 3.6V 2μs/DIV 3548-1 G02 IN = 3.6V VIN = 3.6V 20μs/DIV V V OUT1 = 1.8V OUT2 = 1.575V VOUT1 = 1.8V I I LOAD = 60mA LOAD = 40mA TO 400mA ILOAD = 80mA TO 800mA CHANNEL 1; CIRCUIT OF FIGURE 3 CHANNEL 2; CIRCUIT OF FIGURE 3 CHANNEL 1; CIRCUIT OF FIGURE 3 35481fc 3