Datasheet LT3508 (Analog Devices) - 8

LT3508
OPERATION
The LT3508 is a dual constant frequency, current mode between the two modes. Unique circuitry generates the regulator with internal power switches. Operation can be appropriate slope compensation ramps and generates the best understood by referring to the Block Diagram. If the 180° out-of-phase clocks for the two channels. SHDN pin is tied to ground, the LT3508 is shut down and The switching regulator performs frequency foldback draws minimal current from the input source tied to the during overload conditions. An amplifi er senses when VIN pins. If the SHDN pin exceeds 1V, the internal bias V circuits turn on, including the internal regulator, reference FB is less than 0.625V and begins decreasing the oscil- lator frequency down from full frequency to 12% of the and oscillator. The switching regulators will only begin to nominal frequency when V operate when the SHDN pin exceeds 2.63V. FB = 0V. The FB pin is less than 0.8V during start-up, short-circuit and overload conditions. The switcher is a current mode regulator. Instead of directly Frequency foldback helps limit switch current under these modulating the duty cycle of the power switch, the feedback conditions. loop controls the peak current in the switch during each The switch driver operates either from V cycle. Compared to voltage mode control, current mode IN or from the BOOST pin. An external capacitor and Schottky diode are control improves loop dynamics and provides cycle-by- used to generate a voltage at the BOOST pin that is higher cycle current limit. A pulse from the oscillator sets the than the input supply. This allows the driver to saturate the RS fl ip-fl op and turns on the internal NPN power switch. internal bipolar NPN power switch for effi cient operation. Current in the switch and the external inductor begins to increase. When this current exceeds a level determined The TRACK/SS pin serves as an alternative input to the by the voltage at VC, current comparator C1 resets the error amplifi er. The amplifi er will use the lowest voltage of fl ip-fl op, turning off the switch. The current in the inductor either the reference of 0.8V or the voltage on the TRACK/ fl ows through the external Schottky diode and begins to SS pin as the positive input of error amplifi er. Since the decrease. The cycle begins again at the next pulse from the TRACK/SS pin is driven by a constant current source, a oscillator. In this way, the voltage on the VC pin controls single capacitor on the pin will generate a linear ramp on the current through the inductor to the output. The internal the output voltage. Tying the TRACK/SS pin to a resistor error amplifi er regulates the output current by continually divider from the output of one of the switching regulators adjusting the VC pin voltage. The threshold for switching allows one output to track another. on the VC pin is 0.8V, and an active clamp of 1.75V limits The PG output is an open-collector transistor that is off the output current. when the output is in regulation, allowing an external re- The switching frequency is set either by the resistance to sistor to pull the PG pin high. Power good is valid when GND at the RT/SYNC pin or the frequency of the logic-level the LT3508 is enabled (SHDN is high) and VIN1 is greater signal driving the RT/SYNC pin. A detection circuit monitors than 3.7V. for the presence of a SYNC signal on the pin and switches 3508fd 8 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM OPERATION APPLICATIONS INFORMATION TYPICAL APPLICATIONS PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS