Datasheet LTC3410B (Analog Devices) - 10

LTC3410B
U U W U APPLICATIO S I FOR ATIO Efficiency Considerations
charge, dQ, moves from VIN to ground. The resulting dQ/dt is the current out of V The efficiency of a switching regulator is equal to the IN that is typically larger than the DC bias current. In continuous mode, output power divided by the input power times 100%. It is I often useful to analyze individual losses to determine what GATECHG = f(QT + QB) where QT and QB are the gate charges of the internal top and bottom is limiting the efficiency and which change would produce switches. Both the DC bias and gate charge the most improvement. Efficiency can be expressed as: losses are proportional to VIN and thustheir effectswill Efficiency = 100% – (L1 + L2 + L3 + ...) be more pronounced at higher supply voltages. where L1, L2, etc. are the individual losses as a percentage 2. I2R losses are calculated from the resistances of the of input power. internal switches, RSW, and external inductor RL. In Although all dissipative elements in the circuit produce continuous mode, the average output current flowing losses, two main sources usually account for most of the through inductor L is “chopped” between the main losses in LTC3410B circuits: V switch and the synchronous switch. Thus, the series IN quiescent current and I2R losses. The V resistance looking into the SW pin is a function of both IN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R top and bottom MOSFET RDS(ON) and the duty cycle loss dominates the efficiency loss at medium to high load (DC) as follows: currents. In a typical efficiency plot, the efficiency curve at RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) very low load currents can be misleading since the actual The R power lost is of no consequence as illustrated in Figure 3. DS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Charateristics 1. The VIN quiescent current is due to two components: curves. Thus, to obtain I2R losses, simply add RSW to the DC bias current as given in the electrical character- RL and multiply the result by the square of the average istics and the internal main switch and synchronous output current. switch gate charge currents. The gate charge current Other losses including C results from switching the gate capacitance of the IN and COUT ESR dissipative losses and inductor core losses generally account for less internal power MOSFET switches. Each time the gate is than 2% total additional loss. switched from high to low to high again, a packet of 1 0.1 0.01 POWER LOST (W) 0.001 VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V 0.0001 0.1 1 10 100 1000 LOAD CURRENT (mA) 3410 F03
Figure 3. Power Lost vs Load Current
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