Datasheet LTC3548-2 (Analog Devices) - 10

LTC3548-2
APPLICATIONS INFORMATION
Great care must be taken when using only ceramic input Keeping the current small (<5μA) in these resistors maxi- and output capacitors. When a ceramic capacitor is used mizes effi ciency, but making them too small may allow at the input and the power is being supplied through long stray capacitance to cause noise problems and reduce the wires, such as from a wall adapter, a load step at the output phase margin of the error amp loop. can induce ringing at the VIN pin. At best, this ringing can To improve the frequency response, a feed forward capaci- couple to the output and be mistaken as loop instability. tor C At worst, the ringing at the input can be large enough to F may also be used. Great care should be taken to route the V damage the part. OUT1, VFB2 line away from noise sources, such as the inductor or the SW line. Since the ESR of a ceramic capacitor is so low, the input and output capacitor must instead fulfi ll a charge storage
Power-On Reset
requirement. During a load step, the output capacitor must The POR pin is an open-drain output which pulls low when instantaneously supply the current to support the load either regulator is out of regulation. When both output until the feedback loop raises the switch current enough voltages are above –8.5% of regulation, a timer is started to support the load. The time required for the feedback which releases POR after 218 clock cycles (about 117ms loop to respond is dependent on the compensation and the in pulse-skipping mode). This delay can be signifi cantly output capacitor size. Typically, 3 to 4 cycles are required to longer in Burst Mode operation with low load currents, respond to a load step, but only in the fi rst cycle does the since the clock cycles only occur during a burst and there output drop linearly. The output droop, VDROOP, is usually could be milliseconds of time between bursts. This can about 2 to 3 times the linear drop of the fi rst cycle. Thus, be bypassed by tying the POR output to the MODE/SYNC a good place to start is with the output capacitor size of input, to force pulse-skipping mode during a reset. In ad- approximately: dition, if the output voltage faults during Burst Mode sleep, I Δ POR could have a slight delay for an undervoltage output C OUT OUT ≈ 2 5 . f •V condition. This can be avoided by using pulse-skipping O DROOP mode instead. When either channel is shut down, the POR More capacitance may be required depending on the duty output is pulled low, since one or both of the channels are cycle and load step requirements. not in regulation. In most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance
Mode Selection and Frequency Synchronization
to the supply is very low. A 10μF ceramic capacitor is The MODE/SYNC pin is a multipurpose pin which provides usually enough for these conditions. mode selection and frequency synchronization. Connect- ing this pin to V
Setting the Output Voltage for Channel 2
IN enables Burst Mode operation, which provides the best low current effi ciency at the cost of a The LTC3548-2 develops a 0.6V reference voltage be- higher output voltage ripple. Connecting this pin to ground tween the feedback pin, VFB2, and the ground as shown selects pulse-skipping mode, which provides the lowest in Figure 2. The output voltage, VOUT2, is set by a resistive output ripple, at the cost of low current effi ciency. divider according to the following formula: The LTC3548-2 can also be synchronized to an external ⎛ R2⎞ 2.25MHz clock signal by the MODE/SYNC pin. During V = . V + synchronization, the mode is set to pulse-skipping and OUT2 0 6 1 ⎝⎜ R1⎠⎟ the top switch turn-on is synchronized to the rising edge of the external clock. 35482fb 10