Datasheet LTC3414 (Analog Devices) - 7

LTC3414
U OPERATIO
ing harmonics out of a signal band. The output voltage During synchronization, the burst clamp is set to 0V, and ripple is minimized in this mode. each switching cycle begins at the falling edge of the clock signal.
Burst Mode Operation Dropout Operation
Connecting the SYNC/MODE pin to a voltage in the range of 0V to 1V enables Burst Mode operation. In Burst Mode When the input supply voltage decreases toward the operation, the internal power MOSFETs operate intermit- output voltage, the duty cycle increases toward the maxi- tently at light loads. This increases efficiency by minimiz- mum on-time. Further reduction of the supply voltage ing switching losses. During Burst Mode operation, the forces the main switch to remain on for more than one minimum peak inductor current is externally set by the cycle eventually reaching 100% duty cycle. The output voltage on the SYNC/MODE pin and the voltage on the ITH voltage will then be determined by the input voltage minus pin is monitored by the burst comparator to determine the voltage drop across the internal P-channel MOSFET when sleep mode is enabled and disabled. When the and the inductor. average inductor current is greater than the load current, the voltage on the I
Low Supply Operation
TH pin drops. As the ITH voltage falls below 150mV, the burst comparator trips and enables The LTC3414 is designed to operate down to an input sleep mode. During sleep mode, the top power MOSFET is supply voltage of 2.25V. One important consideration held off and the ITH pin is disconnected from the output of at low input supply voltages is that the RDS(ON) of the the error amplifier. The majority of the internal circuitry is P-channel and N-channel power switches increases. The also turned off to reduce the quiescent current to 64μA user should calculate the power dissipation when the while the load current is solely supplied by the output LTC3414 is used at 100% duty cycle with low input capacitor. When the output voltage drops, the ITH pin is voltages to ensure that thermal limits are not exceeded. reconnected to the output of the error amplifier and the top power MOSFET along with all the internal circuitry is
Slope Compensation and Inductor Peak Current
switched back on. This process repeats at a rate that is dependent on the load demand. Slope compensation provides stability in constant fre- quency architectures by preventing subharmonic oscilla- Pulse Skipping operation is implemented by connecting tions at duty cycles greater than 50%. It is accomplished the SYNC/MODE pin to ground. This forces the burst internally by adding a compensating ramp to the inductor clamp level to be at 0V. As the load current decreases, the current signal at duty cycles in excess of 40%. Normally, peak inductor current will be determined by the voltage on the maximum inductor peak current is reduced when the ITH pin until the ITH voltage drops below 400mV. At this slope compensation is added. In the LTC3414, however, point, the peak inductor current is determined by the slope compensation recovery is implemented to keep the minimum on-time of the current comparator. If the load maximum inductor peak current constant throughout the demand is less than the average of the minimum on-time range of duty cycles. This keeps the maximum output inductor current, switching cycles will be skipped to keep current relatively constant regardless of duty cycle. the output voltage in regulation.
Short-Circuit Protection Frequency Synchronization
When the output is shorted to ground, the inductor current The internal oscillator of the LTC3414 can be synchronized decays very slowly during a single switching cycle. To to an external clock connected to the SYNC/MODE pin. The prevent current runaway from occurring, a secondary frequency of the external clock can be in the range of current limit is imposed on the inductor current. If the 300kHz to 4MHz. For this application, the oscillator timing inductor valley current increases larger than 7.8A, the top resistor should be chosen to correspond to a frequency power MOSFET will be held off and switching cycles will be that is 25% lower than the synchronization frequency. skipped until the inductor current is reduced. 3414fb 7