Datasheet LTC3406, LTC3406-1.5, LTC3406-1.8 (Analog Devices) - 10

LTC3406 LTC3406-1.5/LTC3406-1.8
U U W U APPLICATIO S I FOR ATIO
Although all dissipative elements in the circuit produce 2. I2R losses are calculated from the resistances of the losses, two main sources usually account for most of the internal switches, RSW, and external inductor RL. In losses in LTC3406 circuits: VIN quiescent current and I2R continuous mode, the average output current flowing losses. The VIN quiescent current loss dominates the through inductor L is “chopped” between the main efficiency loss at very low load currents whereas the I2R switch and the synchronous switch. Thus, the series loss dominates the efficiency loss at medium to high load resistance looking into the SW pin is a function of both currents. In a typical efficiency plot, the efficiency curve at top and bottom MOSFET RDS(ON) and the duty cycle very low load currents can be misleading since the actual (DC) as follows: power lost is of no consequence as illustrated in Figure 4. RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) 1 The RDS(ON) for both the top and bottom MOSFETs can VOUT = 1.2V be obtained from the Typical Performance Charateristics VOUT = 1.5V V 0.1 OUT = 1.8V curves. Thus, to obtain I2R losses, simply add RSW to VOUT = 2.5V RL and multiply the result by the square of the average 0.01 output current. Other losses including CIN and COUT ESR dissipative 0.001 POWER LOSS (W) losses and inductor core losses generally account for less than 2% total additional loss. 0.0001
Thermal Considerations
0.00001 0.1 1 10 100 1000 LOAD CURRENT (mA) In most applications the LTC3406 does not dissipate 3406 F04 much heat due to its high efficiency. But, in applications
Figure 4. Power Lost vs Load Current
where the LTC3406 is running at high ambient tempera- ture with low supply voltage and high duty cycles, such 1. The V as in dropout, the heat dissipated may exceed the maxi- IN quiescent current is due to two components: the DC bias current as given in the electrical character- mum junction temperature of the part. If the junction istics and the internal main switch and synchronous temperature reaches approximately 150°C, both power switch gate charge currents. The gate charge current switches will be turned off and the SW node will become results from switching the gate capacitance of the high impedance. internal power MOSFET switches. Each time the gate is To avoid the LTC3406 from exceeding the maximum switched from high to low to high again, a packet of junction temperature, the user will need to do some charge, dQ, moves from VIN to ground. The resulting thermal analysis. The goal of the thermal analysis is to dQ/dt is the current out of VIN that is typically larger than determine whether the power dissipated exceeds the the DC bias current. In continuous mode, IGATECHG = maximum junction temperature of the part. The tempera- f(QT + QB) where QT and QB are the gate charges of the ture rise is given by: internal top and bottom switches. Both the DC bias and TR = (PD)(θJA) gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply where PD is the power dissipated by the regulator and θJA voltages. is the thermal resistance from the junction of the die to the ambient temperature. 3406fa 10