Datasheet LTC3405A (Analog Devices) - 10

LTC3405A
U U W U APPLICATIO S I FOR ATIO
Although all dissipative elements in the circuit produce 2. I2R losses are calculated from the resistances of the losses, two main sources usually account for most of the internal switches, RSW, and external inductor RL. In losses in LTC3405A circuits: VIN quiescent current and I2R continuous mode, the average output current flowing losses. The VIN quiescent current loss dominates the through inductor L is “chopped” between the main efficiency loss at very low load currents whereas the I2R switch and the synchronous switch. Thus, the series loss dominates the efficiency loss at medium to high load resistance looking into the SW pin is a function of both currents. In a typical efficiency plot, the efficiency curve at top and bottom MOSFET RDS(ON) and the duty cycle very low load currents can be misleading since the actual (DC) as follows: power lost is of no consequence as illustrated in Figure 4. RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) 1 The RDS(ON) for both the top and bottom MOSFETs can VIN = 3.6V be obtained from the Typical Performance Charateristics curves. Thus, to obtain I2R losses, simply add RSW to 0.1 RL and multiply the result by the square of the average VOUT = 1.8V output current. 0.01 Other losses including CIN and COUT ESR dissipative POWER LOST (W) losses and inductor core losses generally account for less VOUT = 3.3V V 0.001 OUT = 2.5V than 2% total additional loss. VOUT = 1.3V
Thermal Considerations
0.0001 0.1 1 10 100 1000 LOAD CURRENT (mA) In most applications the LTC3405A does not dissipate 3405A F04 much heat due to its high efficiency. But, in applications where the LTC3405A is running at high ambient
Figure 4. Power Lost vs Load Current
temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may 1. The V exceed the maximum junction temperature of the part. If IN quiescent current is due to two components: the DC bias current as given in the electrical character- the junction temperature reaches approximately 150°C, istics and the internal main switch and synchronous both power switches will be turned off and the SW node switch gate charge currents. The gate charge current will become high impedance. results from switching the gate capacitance of the To avoid the LTC3405A from exceeding the maximum internal power MOSFET switches. Each time the gate is junction temperature, the user will need to do some switched from high to low to high again, a packet of thermal analysis. The goal of the thermal analysis is to charge, dQ, moves from VIN to ground. The resulting determine whether the power dissipated exceeds the dQ/dt is the current out of VIN that is typically larger than maximum junction temperature of the part. The tempera- the DC bias current. In continuous mode, IGATECHG = ture rise is given by: f(QT + QB) where QT and QB are the gate charges of the TR = (PD)(θJA) internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VIN and thus where PD is the power dissipated by the regulator and θJA their effects will be more pronounced at higher supply is the thermal resistance from the junction of the die to the voltages. ambient temperature. 3405afa 10