Datasheet LT1765, LT1765-1.8, LT1765-2.5, LT1765-3.3, LT1765-5 (Analog Devices) - 6

LT1765/LT1765-1.8/LT1765-2.5/ LT1765-3.3/LT1765-5
PIN FUNCTIONS FB:
The feedback pin is used to set output voltage using
VSW:
The switch pin is the emitter of the on-chip power an external voltage divider (adjustable version) that gener- NPN switch. This pin is driven up to the input pin voltage ates 1.2V at the pin when connected to the desired output during switch on time. Inductor current drives the switch voltage. The fi xed voltage 1.8V, 2.5V, 3.3V and 5V versions pin negative during switch off time. Negative voltage must have the divider network included internally and the FB pin be clamped with an external catch diode with a VBR <0.8V. is connected directly to the output. If required, the current Both VSW pins of the TSSOP package must be shorted limit can be reduced during start up or short-circuit when together on the PC board. the FB pin is below 0.5V (see the Current Limit Foldback
SYNC:
The sync pin is used to synchronize the internal graph in the Typical Performance Characteristics section). oscillator to an external signal. It is directly logic compat- An impedance of less than 5kΩ on the adjustable version ible and can be driven with any signal between 20% and at the FB pin is needed for this feature to operate. 80% duty cycle. The synchronizing range is from 1.6MHz
BOOST:
The BOOST pin is used to provide a drive voltage, to 2MHz. See Synchronization section in Applications higher than the input voltage, to the internal bipolar NPN Information for details. When not in use, this pin should power switch. be grounded.
VIN:
This is the collector of the on-chip power NPN switch.
SHDN:
The shutdown pin is used to turn off the regula- This pin powers the internal circuitry and internal regulator. tor and to reduce input drain current to a few microam- At NPN switch on and off, high di/dt edges occur on this peres. The 1.33V threshold can function as an accurate pin. Keep the external bypass capacitor and catch diode undervoltage lockout (UVLO), preventing the regulator close to this pin. All trace inductance on this path will from operating until the input voltage has reached a pre- create a voltage spike at switch off, adding to the VCE volt- determined level. Float or pull high to put the regulator in age across the internal NPN. Both VIN pins of the TSSOP the operating mode. package must be shorted together on the PC board.
VC:
The VC pin is the output of the error amplifi er and the
GND:
The GND pin acts as the reference for the regulated input of the peak switch current comparator. It is normally output, so load regulation will suffer if the “ground” end of used for frequency compensation, but can do double duty the load is not at the same voltage as the GND pin of the as a current clamp or control loop override. This pin sits IC. This condition will occur when load current or other at about 0.4V for very light loads and 0.9V at maximum currents fl ow through metal paths between the GND pin load. It can be driven to ground to shut off the output. and the load ground point. Keep the ground path short between the GND pin and the load and use a ground plane when possible. Keep the path between the input bypass and the GND pin short. The exposed GND pad and/or GND pins of the package are directly attached to the internal tab. These pins/pad should be attached to a large copper area to reduce thermal resistance. 1765fd 6