Datasheet LTC1877 (Analog Devices) - 8

LTC1877
OPERATION (Refer to Functional Diagram)
The LTC1877 uses a constant-frequency, current mode then disconnected from the output of the EA amplifi er and step-down architecture. Both the main (P-channel MOS- parked a diode voltage above ground. FET) and synchronous (N-channel MOSFET) switches are In sleep mode, both power MOSFETs are held off and a internal. During normal operation, the internal top power majority of the internal circuitry is partially turned off, MOSFET is turned on each cycle when the oscillator sets reducing the quiescent current to 10μA. The load current the RS latch, and turned off when the current comparator, is now being supplied solely from the output capacitor. ICOMP, resets the RS latch. The peak inductor current at When the output voltage drops, the I which I TH pin reconnects COMP resets the RS latch is controlled by the volt- to the output of the EA amplifi er and the top MOSFET is age on the ITH pin, which is the output of error amplifi er again turned on and this process repeats. EA. The VFB pin, described in the Pin Functions section, allows EA to receive an output feedback voltage from an
Short-Circuit Protection
external resistive divider. When the load current increases, it causes a slight decrease in the feedback voltage relative When the output is shorted to ground, the frequency of to the 0.8V reference, which in turn, causes the I the oscillator is reduced to about 80kHz, one-seventh the TH voltage to increase until the average inductor current matches the nominal frequency. This frequency foldback ensures that new load current. While the top MOSFET is off, the bottom the inductor current has ample time to decay, thereby MOSFET is turned on until either the inductor current starts preventing runaway. The oscillator’s frequency will progres- to reverse as indicated by the current reversal comparator sively increase to 550kHz (or the synchronized frequency) I when V RCMP, or the beginning of the next clock cycle. FB rises above 0.3V. Comparator OVDET guards against transient overshoots
Frequency Synchronization
> 6.25% by turning the main switch off and keeping it off A phase-locked loop (PLL) is available on the LTC1877 to until the fault is removed. allow the internal oscillator to be synchronized to an external
Burst Mode Operation
source connected to the SYNC/MODE pin. The output of the phase detector at the PLL LPF pin operates over a 0V The LTC1877 is capable of Burst Mode operation in which to 2.4V range corresponding to 400kHz to 700kHz. When the internal power MOSFETs operate intermittently based locked, the PLL aligns the turn-on of the top MOSFET to on load demand. To enable Burst Mode operation, simply the rising edge of the synchronizing signal. tie the SYNC/MODE pin to VIN or connect it to a logic high (V When the LTC1877 is clocked by an external source, Burst SYNC/MODE > 1.5V). To disable Burst Mode opera- tion and enable PWM pulse-skipping mode, connect the Mode operation is disabled; the LTC1877 then operates in SYNC/MODE pin to GND. In this mode, the effi ciency is PWM pulse-skipping mode. In this mode, when the output lower at light loads, but becomes comparable to Burst load is very low, current comparator ICOMP may remain Mode operation when the output load exceeds 50mA. The tripped for several cycles and force the main switch to stay advantage of pulse-skipping mode is lower output ripple off for the same number of cycles. Increasing the output and less interference to audio circuitry. load slightly allows constant-frequency PWM operation to resume. This mode exhibits low output ripple as well When the converter is in Burst Mode operation, the peak as low audio noise and reduced RF interference while current of the inductor is set to approximately 250mA, providing reasonable low current effi ciency. even though the voltage at the ITH pin indicates a lower value. The voltage at the I Frequency synchronization is inhibited when the feedback TH pin drops when the inductor’s average current is greater than the load requirement. As the voltage VFB is below 0.6V. This prevents the external clock I from interfering with the frequency foldback for short- TH voltage drops below approximately 0.55V, the BURST comparator trips, causing the internal sleep line to go circuit protection. high and forces off both power MOSFETs. The ITH pin is 1877fb 8