Datasheet LTC3838 (Analog Devices) - 10

LTC3838
pin FuncTions (QFN/TSSOP) PHASMD (Pin 4/Pin 8):
Phase Selector Input. This pin
VRNG1, VRNG2 (Pins 9, 3/Pins 13, 7):
Current Sense Volt- determines the relative phases of channels and the age Range Inputs. When programmed between 0.6V and CLKOUT signal. With zero phase being defined as the 2V, the voltage applied to VRNG1,2 is twenty times (20×) rising edge of TG1: Pulling this pin to SGND locks TG2 to the maximum sense voltage between SENSE1,2+ and 180°, and CLKOUT to 60°. Connecting this pin to INTV + – CC SENSE1,2–, i.e., for either channel, (VSENSE – VSENSE ) = locks TG2 to 240° and CLKOUT to 120°. Floating this pin 0.05 • VRNG. If a VRNG is tied to SGND, the channel oper- locks TG2 to 180° and CLKOUT to 90°. ates with a maximum sense voltage of 30mV, equivalent
MODE/PLLIN (Pin 5/Pin 9):
Operation Mode Selection to a VRNG of 0.6V; If tied to INTVCC, a maximum sense or External Clock Synchronization Input. When this pin voltage of 50mV, equivalent to a VRNG of 1V. is tied to INTVCC, forced continuous mode operation is
ITH1, ITH2 (Pins 10, 2/Pins 14, 6):
Current Control selected. Tying this pin to SGND allows discontinuous Threshold. This pin is the output of the error amplifier and mode operation. When an external clock is applied at this the switching regulator’s compensation point. The current pin, both channels operate in forced continuous mode and comparator threshold increases with this control voltage. synchronize to the external clock. The voltage ranges from 0V to 2.4V, with 0.8V correspond-
CLKOUT (Pin 6/Pin 10):
Clock Output of Internal Clock ing to zero sense voltage (zero inductor valley current). Generator. Its output level swings between INTVCC and
TRACK/SS1, TRACK/SS2 (Pins 11, 1/Pins 15, 5):
External SGND. If clock input is present at the MODE/PLLIN pin, it Tracking and Soft-Start Input. The LTC3838 regulates the will be synchronized to the input clock, with phase set by feedback voltages (V + – OUTSENSE1 – VOUTSENSE1 ) and VFB2 the PHASMD pin. If no clock is present at MODE/PLLIN, its to the smaller of 0.6V or the voltage on the TRACK/SS1,2 frequency will be set by the RT pin. To synchronize other pins respectively. An internal 1µA temperature-independent controllers, it can be connected to their MODE/PLLIN pins. pull-up current source is connected to each TRACK/SS
SGND (Pin 7/Pin 11):
Signal Ground. All small-signal analog pin. A capacitor to ground at this pin sets the ramp time and compensation components should be connected to to the final regulated output voltage. Alternatively, another this ground. Connect SGND to the exposed pad and PGND voltage supply connected to this pin allows the output to pin using a single PCB trace. track the other supply during start-up.
+ RT (Pin 8/Pin 12):
Clock Generator Frequency Program-
VOUTSENSE1 (Pin 12/Pin 16):
Differential Output Sense ming Pin. Connect an external resistor from RT to SGND Amplifier (+) Input of Channel 1. Connect this pin to a to program the switching frequency between 200kHz and feedback resistor divider between the positive and negative 2MHz. An external clock applied to MODE/PLLIN should output capacitor terminals of VOUT1. In nominal operation be within ±30% of this programmed frequency to ensure the LTC3838 will attempt to regulate the differential output frequency lock. When the RT pin is floating, the frequency voltage VOUT1 to 0.6V divided by the feedback resistor is internally set to be slightly under 200kHz. divider ratio. 3838fb 10 For more information www.linear.com/LTC3838 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Typical Applications Package Description Revision History Typical Application Related Parts