Datasheet ADP1876 (Analog Devices) - 8

ADP1876 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 1 1 D 1 P P O 1 1 K 1 M M 1 IM T TR FB CO RA SS PGO IL BS 32 31 30 29 28 27 26 25 EN1 1 24 SW1 VIN 2 23 DH1 VINLDO 3 22 PGND1 ADP1876 VOUTLDO 4 21 DL1 TOP VIEW VCCO 5 20 DL2 (Not to Scale) VDL 6 19 PGND2 AGND 7 18 DH2 NC 8 17 SW2 9 10 11 12 13 14 15 16 2 2 2 2 2 2 2 2 P P D T EN FB M SS O IM O IL BS CO RAM PG NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
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2. CONNECT THE BOTTOM EXPOSED PAD OF THE
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LFCSP PACKAGE TO SYSTEM AGND PLANE.
103- 10 Figure 3. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1 EN1 Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 controller, and drive it low to turn it off. Tie EN1 to VIN for automatic startup. For a precision UVLO, put an appropriately sized resistor divider from VIN to AGND and tie the midpoint to this pin. 2 VIN Connect to Main Power Supply. Bypass with a 1 μF or larger ceramic capacitor connected as close to this pin as possible and PGNDx. 3 VINLDO Input for Independent Linear Dropout (LDO) Regulator. 4 VOUTLDO Output for Independent LDO Regulator. 5 VCCO Output of the Internal LDO. The internal circuitry and gate drivers are powered from VCCO. Bypass VCCO to AGND with a 1 μF or larger ceramic capacitor. The VCCO output is always active, even during fault conditions, and it cannot be turned off even when EN1 or EN2 is low. For operation at VIN below 5 V, VIN can be jumped to VCCO. Do not use the VCCO to power any other auxiliary system load. 6 VDL Power Supply for the Low-Side Driver. Bypass VDL to PGNDx with a 1 μF ceramic capacitor. Connect VCCO to VDL. 7 AGND Analog Ground. 8 NC No connect. Do not connect to this pin. 9 EN2 Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 controller, and drive it low to turn off. Tie EN2 to VIN for automatic startup. For a precision UVLO, put an appropriately sized resistor divider from VIN to AGND and tie the midpoint to this pin. 10 FB2 Output Voltage Feedback for Channel 2. 11 COMP2 Compensation Node for Channel 2. Output of the Channel 2 error amplifier. Connect a series resistor/capacitor network from COMP2 to AGND to compensate the regulation control loop. 12 RAMP2 Programmable Current Setting for Slope Compensation of Channel 2. Connect a resistor from RAMP2 to VIN. The voltage at RAMP2 is 0.2 V during operation. This pin is high impedance when the channel is disabled. 13 SS2 Soft Start Input for Channel 2. Connect a capacitor from SS2 to AGND to set the soft start period. This node is internally pulled up to 3.2 V through a 6.5 μA current source. 14 PGOOD2 Open-Drain Power-Good Indicator Logic Output at PGOOD2. An internal 12 kΩ resistor is connected between PGOOD2 and VCCO. PGOOD2 is pulled to ground when the Channel 2 output is outside the regulation window. An external pull-up resistor is not required. 15 ILIM2 Current-Limit Sense Comparator Inverting Input for Channel 2. Connect a resistor between ILIM2 and SW2 to set the current-limit offset. For accurate current-limit sensing, connect ILIM2 to a current sense resistor at the source of the low-side MOSFET. 16 BST2 Boot Strapped Upper Rail of High-Side Internal Driver for Channel 2. Connect a 0.1 μF to 0.22 μF multilayer ceramic capacitor (MLCC) between BST2 and SW2. There is an internal boost rectifier connected between VDL and BST2. 17 SW2 Switch Node for Channel 2. Connect to the source of the high-side N-channel MOSFET and the drain of the low- side N-channel MOSFET of Channel 2. 18 DH2 High-Side Switch Gate Driver Output for Channel 2. Rev. B | Page 8 of 24 Document Outline FEATURES APPLICATIONS TYPICAL OPERATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INDEPENDENT LOW DROPOUT LINEAR REGULATOR CONTROLLER ARCHITECTURE Synchronous Rectifier and Dead Time INPUT UNDERVOLTAGE LOCKOUT INTERNAL LINEAR REGULATOR (VCCO) OVERVOLTAGE PROTECTION POWER GOOD SHORT-CIRCUIT AND CURRENT-LIMIT PROTECTION SHUTDOWN CONTROL THERMAL OVERLOAD PROTECTION APPLICATIONS INFORMATION INDEPENDENT LOW DROPOUT LINEAR REGULATOR SETTING THE OUTPUT VOLTAGE OF THE CONTROLLER SOFT START SETTING THE CURRENT LIMIT ACCURATE CURRENT-LIMIT SENSING SETTING THE SLOPE COMPENSATION SETTING THE CURRENT SENSE GAIN INPUT CAPACITOR SELECTION INPUT FILTER BOOST CAPACITOR SELECTION INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION MOSFET SELECTION LOOP COMPENSATION SWITCHING NOISE AND OVERSHOOT REDUCTION PCB LAYOUT GUIDELINE TYPICAL APPLICATIONS CIRCUIT PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE