Datasheet ADP1850 (Analog Devices) - 7

Data Sheet ADP1850 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 1 P 1 1 MP1 T RK1 B1 O GOOD T F C RAM SS1 P ILIM BS 32 31 30 29 28 27 26 25 EN1 1 24 SW1 SYNC 2 23 DH1 VIN 3 22 PGND1 ADP1850 VCCO 4 21 DL1 TOP VIEW VDL 5 20 DL2 (Not to Scale) AGND 6 19 PGND2 FREQ 7 18 DH2 EN2 8 17 SW2 9 1 10 1 12 13 14 15 16 2 2 2 2 B2 P T RK2 F MP2 SS2 T O ILIM BS C RAM GOOD P NOTES
004
1. CONNECT THE BOTTOM EXPOSED PAD OF THE LFCSP PACKAGE TO SYSTEM AGND PLANE.
09440- Figure 3. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1 EN1 Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 controller, and drive EN1 low to turn off the Channel 1 controller. Tie EN1 to VIN for automatic startup. For a precision UVLO, put an appropriately sized resistor divider from VIN to AGND and tie the midpoint to this pin. 2 SYNC Frequency Synchronization Input. Accepts an external signal between 1× and 2.3× of the internal oscillator frequency, f , set by the FREQ pin. The controller operates in forced PWM when a signal is detected at SYNC or SW when SYNC is high. The resulting switching frequency is ½ of the SYNC frequency. When SYNC is low or left floating, the controller operates in pulse skip mode. For dual-phase operation, connect SYNC to a logic high or an external clock. 3 VIN Connect to Main Power Supply. Bypass with a 1 µF or larger ceramic capacitor connected as close to this pin as possible and PGNDx. 4 VCCO Output of the Internal Low Dropout Regulator (LDO). Bypass VCCO to AGND with a 1 μF or larger ceramic capacitor. The VCCO output remains active even when EN1 and EN2 are low. For operation with VIN below 5 V, VIN may be shorted to VCCO. Do not use the LDO to power other auxiliary system loads. 5 VDL Power Supply for the Low-Side Driver. Bypass VDL to PGNDx with a 1 µF or greater ceramic capacitor. Connect VCCO to VDL. 6 AGND Analog Ground. 7 FREQ Sets the desired operating frequency between 200 kHz and 1.5 MHz with one resistor between FREQ and AGND. Connect FREQ to AGND for a preprogrammed 300 kHz or FREQ to VCCO for 600 kHz operating frequency. 8 EN2 Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 controller, and drive EN2 low to turn off the Channel 2 controller. Tie EN2 to VIN for automatic startup. For a precision UVLO, put an appropriately sized resistor divider from VIN to AGND, and tie the midpoint to this pin. 9 TRK2 Tracking Input for Channel 2. Connect TRK2 to VCCO if tracking is not used. 10 FB2 Output Voltage Feedback for Channel 2. Connect to Output 2 via a resistor divider. 11 COMP2 Compensation Node for Channel 2. Output of Channel 2 error amplifier. Connect a series resistor-capacitor network from COMP2 to AGND to compensate the regulation control loop. 12 RAMP2 Connect a resistor from RAMP2 to VIN to set up a ramp current for slope compensation in Channel 2. The voltage at RAMP2 is 0.2 V. This pin is high impedance when the channel is disabled. 13 SS2 Soft Start Input for Channel 2. Connect a capacitor from SS2 to AGND to set the soft start period. The node is internally pulled up to 5 V with a 6.5 µA current source. 14 PGOOD2 Power Good. Open-drain power-good indicator logic output with an internal 12 kΩ resistor connected between PGOOD2 and VCCO. PGOOD2 is pulled to ground when the Channel 2 output is outside the regulation window. An external pull-up resistor is not required. Rev. C | Page 7 of 32 Document Outline Features Applications General Description Typical Operation Circuit Revision History Specifications Absolute Maximum Ratings ESD Caution Simplified Block Diagram Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Control Architecture Oscillator Frequency Modes of Operation Synchronization Synchronous Rectifier and Dead Time Input Undervoltage Lockout Internal Linear Regulator Overvoltage Protection Power Good Short-Circuit and Current-Limit Protection Shutdown Control Thermal Overload Protection Applications Information Setting the Output Voltage Soft Start Setting the Current Limit Accurate Current-Limit Sensing Setting the Slope Compensation Setting the Current Sense Gain Input Capacitor Selection Input Filter Boost Capacitor Selection Inductor Selection Output Capacitor Selection MOSFET Selection Loop Compensation (Single Phase Operation) Configuration and Loop Compensation (Dual-Phase Operation) Switching Noise and Overshoot Reduction Voltage Tracking Coincident Tracking Ratiometric Tracking Indepdendent Power Stage Input Voltage PCB Layout Guidelines MOSFETs, Input Bulk Capacitor, and Bypass Capacitor High Current and Current Sense Paths Signal Paths PGND Plane Feedback and Current-Limit Sense Paths Switch Node Gate Driver Paths Output Capacitors Typical Operating Circuits Outline Dimensions Ordering Guide