Datasheet LT3742 (Analog Devices) - 8

LT3742
operaTion
The LT3742 is a dual, constant frequency, current mode A power good comparator pulls the PG pin low whenever DC/DC step-down controller. The two controllers in each the FB pin is not within ±10% of the 800mV internal device share some common circuitry including protec- reference voltage. PG is the open-collector output of an tion circuitry, the internal bias supply, voltage reference, NPN that is off when the FB pin is in regulation, allowing master oscillator and the gate drive boost regulator. The an external resistor to pull the PG pin high. This power Block Diagram shows the shared common circuitry and good indication is valid only when the device is enabled the independent circuitry for both DC/DC controllers. (RUN/SS is high) and VIN is 4V or greater. Important protection features included in the LT3742 are The LT3742 enables each controller independently when its undervoltage lockout and thermal shutdown. When either RUN/SS pin is above 0.5V and each controller generates of these conditions exist, the gate drive bias regulator and its own soft-start ramp. During start-up, the error ampli- both DC/DC controllers are disabled and both RUN/SS pins fier compares the FB pin to the soft-start ramp instead of are discharged to 0.5V to get ready for a new soft-start the precision 800mV reference, which slowly raises the cycle. Undervoltage lockout (UVLO) is programmed using output voltage until it reaches its resistor programmed two external resistors. When the UVLO pin drops below regulation point. Control of the inductor current is strictly 1.25V, a 3µA current sink is activated to provide program- maintained until the output voltage is reached. The LT3742 mable hysteresis for the UVLO function. A separate, less is ideal for applications where both DC/DC controllers need accurate, internal undervoltage lockout will disable the to operate separately. LT3742 when VIN is less than 2.5V. A pulse from the 500kHz oscillator sets the RS flip-flop The gate drive boost regulator is enabled when all internal and turns on the external N-channel MOSFET. Current in fault conditions have been cleared. This regulator uses the switch and the external inductor begins to increase. both an internal NPN power switch and Schottky diode to When this current reaches a level determined by the control generate a voltage at the BIAS pin that is 7V higher than voltage (VC), the PWM comparator resets the flip-flop, the input voltage. Both DC/DC controllers are disabled until turning off the MOSFET. The current in the inductor then the BIAS voltage has reached ~90% of its final regulation flows through the external Schottky diode and begins to voltage. This ensures that sufficient gate drive to fully decrease. This cycle begins again at the next set pulse from enhance the external MOSFETs is present before the driver the slave oscillator. In this way, the voltage at the VC pin is allowed to turn on. controls the current through the inductor to the output. The master oscillator runs at 1MHz and clocks the gate The internal error amplifier regulates the output voltage drive boost regulator at this frequency. The master oscilla- by continually adjusting the VC pin voltage. Direct control tor also generates two 500kHz clocks, 180° out of phase, of the peak inductor current on a cycle-by-cycle basis is for the DC/DC controllers. managed by the current sense amplifier. Because the induc- tor current is constantly monitored, the devices inherently provide excellent output short-circuit protection. 3742fa 8 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Related Parts