Datasheet LTC3826 (Analog Devices) - 8

LTC3826
PIN FUNCTIONS SENSE1–, SENSE2– (Pins 1, 9):
The (–) Input to the
INTVCC (Pin 19):
Output of the Internal Linear Low Dropout Differential Current Comparators. Regulator. The driver and control circuits are powered from this voltage source. Must be decoupled to power
PLLLPF (Pin 2):
The phase-locked loop’s lowpass fi lter is ground with a minimum of 4.7μF tantalum or other low tied to this pin when synchronizing to an external clock. ESR capacitor. Alternatively, tie this pin to GND, INTVCC or leave fl oating to select 250kHz, 530kHz or 390kHz switching frequency.
EXTVCC (Pin 20):
External Power Input to an Internal LDO Connected to INTV
PHASMD (Pin 3):
Control Input to Phase Selector which CC. This LDO supplies INTVCC power, bypassing the internal LDO powered from V determines the phase relationships between controller 1, IN whenever EXTV controller 2 and the CLKOUT signal. CC is higher than 4.7V. See EXTVCC Connection in the Applications Information section. Do not exceed 10V
CLKOUT (Pin 4):
Output Clock Signal available to daisy- on this pin. chain other controller ICs for additional MOSFET driver
PGND (Pin 21):
Driver Power Ground. Connects to the stages/phases. sources of bottom (synchronous) N-channel MOSFETs,
PLLIN/MODE (Pin 5):
External Synchronization Input to anodes of the Schottky rectifi ers and the (–) terminal(s) Phase Detector and Forced Continuous Control Input. When of CIN. an external clock is applied to this pin, the phase-locked
V
loop will force the rising TG1 signal to be synchronized
IN (Pin 22):
Main Supply Pin. A bypass capacitor should be tied between this pin and the signal ground pin. with the rising edge of the external clock. In this case, an R-C fi lter must be connected to the PLLLPF pin. When
BG1, BG2 (Pins 23, 18):
High Current Gate Drives for Bot- not synchronizing to an external clock, this input, which tom (Synchronous) N-Channel MOSFETs. Voltage swing acts on both controllers, determines how the LTC3826 at these pins is from ground to INTVCC. operates at light loads. Pulling this pin below 0.7V selects
BOOST1, BOOST2 (Pins 24, 17):
Bootstrapped Supplies Burst Mode operation. Tying this pin to INTVCC forces to the Top Side Floating Drivers. Capacitors are connected continuous inductor current operation. Tying this pin to between the BOOST and SW pins and Schottky diodes are a voltage greater than 0.9V and less than INTVCC –1.2V tied between the BOOST and INTV selects pulse skipping operation. CC pins. Voltage swing at the BOOST pins is from INTVCC to (VIN + INTVCC).
SGND (Pins 6, 33):
Small Signal Ground common to both
SW1, SW2 (Pins 25, 16):
Switch Node Connections to controllers, must be routed separately from high current Inductors. Voltage swing at these pins is from a Schottky grounds to the common (–) terminals of the CIN capaci- diode (external) voltage drop below ground to V tors. The Exposed Pad is SGND. It must be soldered to IN. PCB ground for rated thermal performance.
TG1, TG2 (Pins 26, 15):
High Current Gate Drives for Top N-Channel MOSFETs. These are the outputs of fl oat-
RUN1, RUN2 (Pins 7, 8):
Digital Run Control Inputs for ing drivers with a voltage swing equal to INTV Each Controller. Forcing either of these pins below 0.7V CC – 0.5V superimposed on the switch node voltage SW. shuts down that controller. Forcing both of these pins below 0.7V shuts down the entire LTC3826, reducing quiescent
PGOOD1 (Pin 27):
Open-Drain Logic Output. PGOOD1 is current to approximately 4μA. pulled to ground when the voltage on the VFB1 pin is not within ±10% of its set point.
FOLDDIS (Pin 14):
Foldback Current Disable Input Pin. Driving this pin high (to INTVCC) disables foldback current limiting during short-circuit or overcurrent conditions. 3826fc 8