Datasheet LTC3727LX-1 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator |
| 页数 / 页 | 28 / 8 — PI FU CTIO S G Package/UH Package RUN/SS1, RUN/SS2 (Pins 1, 15/Pins 28, … |
| 文件格式/大小 | PDF / 431 Kb |
| 文件语言 | 英语 |
PI FU CTIO S G Package/UH Package RUN/SS1, RUN/SS2 (Pins 1, 15/Pins 28, 13):. PGND (Pin 20/Pin 19):. INTV
该数据表的模型线
文件文字版本
LTC3727LX-1
U U U PI FU CTIO S G Package/UH Package RUN/SS1, RUN/SS2 (Pins 1, 15/Pins 28, 13):
Combina-
PGND (Pin 20/Pin 19):
Driver Power Ground. Connects to tion of Soft-Start and Run Control Inputs. A capacitor to the sources of bottom (synchronous) N-channel MOS- ground at each of these pins sets the ramp time to full FETs, anodes of the Schottky rectifiers and the (–) output current. Forcing either of these pins back below terminal(s) of CIN. 1.0V causes the IC to shut down the circuitry required for
INTV
that particular controller.
CC (Pin 21/Pin 20):
Output of the Internal 7.5V Linear Low Dropout Regulator and the EXTVCC Switch. The driver
SENSE1+, SENSE2+ (Pins 2, 14/Pins 30, 12):
The (+) and control circuits are powered from this voltage source. Input to the Differential Current Comparators. The ITH pin Must be decoupled to power ground with a minimum of 4.7µF voltage and controlled offsets between the SENSE– and tantalum or other low ESR capacitor. SENSE+ pins in conjunction with RSENSE set the current
EXTV
trip threshold.
CC (Pin 22/Pin 21):
External Power Input to an Internal Switch Connected to INTVCC. This switch closes
SENSE1–, SENSE2– (Pins 3, 13/Pins 31, 11):
The (–) and supplies VCC power, bypassing the internal low drop- Input to the Differential Current Comparators. out regulator, whenever EXTVCC is higher than 7.3V. See
V
EXTV
OSENSE1, VOSENSE2 (Pins 4, 12/Pins 1, 9):
Receives the CC connection in Applications section. Do not exceed remotely-sensed feedback voltage for each controller from 8.5V on this pin. an external resistive divider across the output.
BG1, BG2 (Pins 23, 19/Pins 22, 18):
High Current Gate
PLLFLTR (Pin 5/Pin 2):
The phase-locked loop’s lowpass Drives for Bottom (Synchronous) N-Channel MOSFETs. filter is tied to this pin. Alternatively, this pin can be driven Voltage swing at these pins is from ground to INTVCC. with an AC or DC voltage source to vary the frequency of
VIN (Pin 24/Pin 23):
Main Supply Pin. A bypass capacitor the internal oscillator. should be tied between this pin and the signal ground pin.
PLLIN (Pin 6/Pin 3):
External Synchronization Input to
BOOST1, BOOST2 (Pins 25, 18/Pins 24, 17):
Bootstrapped Phase Detector. This pin is internally terminated to SGND Supplies to the Top Side Floating Drivers. Capacitors are with 50kΩ. The phase-locked loop will force the rising top connected between the boost and switch pins and Schot- gate signal of controller 1 to be synchronized with the tky diodes are tied between the boost and INTVCC pins. rising edge of the PLLIN signal. Voltage swing at the boost pins is from INTVCC to (VIN +
FCB (Pin 7/Pin 4):
Forced Continuous Control Input. This INTVCC). input acts on both controllers and is normally used to
SW1, SW2 (Pins 26, 17/Pins 25, 15):
Switch Node regulate a secondary winding. Pulling this pin below 0.8V Connections to Inductors. Voltage swing at these pins is will force continuous synchronous operation. Do not from a Schottky diode (external) voltage drop below leave this pin floating. ground to VIN.
ITH1, ITH2 (Pins 8, 11/Pins 5, 8):
Error Amplifier Outputs
TG1, TG2 (Pins 27, 16/Pins 26, 14):
High Current Gate and Switching Regulator Compensation Points. Each as- Drives for Top N-Channel MOSFETs. These are the outputs sociated channels’ current comparator trip point increases of floating drivers with a voltage swing equal to INTVCC – with this control voltage. 0.5V superimposed on the switch node voltage SW.
SGND (Pin 9/Pin 6):
Small Signal Ground. Common
PGOOD (Pin 28/Pin 27):
Open-Drain Logic Output. PGOOD to both controllers; must be routed separately from is pulled to ground when the voltage on either VOSENSE pin high current grounds to the common (–) terminals is not within ±7.5% of its set point. of the COUT capacitors.
Exposed Pad (Pin 33, UH Package):
Signal Ground. Must
3.3VOUT (Pin 10/Pin 7):
Linear Regulator Output. be soldered to the PCB ground for electrical contact and Capable of supplying 10mA DC with peak currents as optimum thermal performance. high as 50mA. 3727lx1fa 8
U U U PI FU CTIO S G Package/UH Package RUN/SS1, RUN/SS2 (Pins 1, 15/Pins 28, 13):
Combina-
PGND (Pin 20/Pin 19):
Driver Power Ground. Connects to tion of Soft-Start and Run Control Inputs. A capacitor to the sources of bottom (synchronous) N-channel MOS- ground at each of these pins sets the ramp time to full FETs, anodes of the Schottky rectifiers and the (–) output current. Forcing either of these pins back below terminal(s) of CIN. 1.0V causes the IC to shut down the circuitry required for
INTV
that particular controller.
CC (Pin 21/Pin 20):
Output of the Internal 7.5V Linear Low Dropout Regulator and the EXTVCC Switch. The driver
SENSE1+, SENSE2+ (Pins 2, 14/Pins 30, 12):
The (+) and control circuits are powered from this voltage source. Input to the Differential Current Comparators. The ITH pin Must be decoupled to power ground with a minimum of 4.7µF voltage and controlled offsets between the SENSE– and tantalum or other low ESR capacitor. SENSE+ pins in conjunction with RSENSE set the current
EXTV
trip threshold.
CC (Pin 22/Pin 21):
External Power Input to an Internal Switch Connected to INTVCC. This switch closes
SENSE1–, SENSE2– (Pins 3, 13/Pins 31, 11):
The (–) and supplies VCC power, bypassing the internal low drop- Input to the Differential Current Comparators. out regulator, whenever EXTVCC is higher than 7.3V. See
V
EXTV
OSENSE1, VOSENSE2 (Pins 4, 12/Pins 1, 9):
Receives the CC connection in Applications section. Do not exceed remotely-sensed feedback voltage for each controller from 8.5V on this pin. an external resistive divider across the output.
BG1, BG2 (Pins 23, 19/Pins 22, 18):
High Current Gate
PLLFLTR (Pin 5/Pin 2):
The phase-locked loop’s lowpass Drives for Bottom (Synchronous) N-Channel MOSFETs. filter is tied to this pin. Alternatively, this pin can be driven Voltage swing at these pins is from ground to INTVCC. with an AC or DC voltage source to vary the frequency of
VIN (Pin 24/Pin 23):
Main Supply Pin. A bypass capacitor the internal oscillator. should be tied between this pin and the signal ground pin.
PLLIN (Pin 6/Pin 3):
External Synchronization Input to
BOOST1, BOOST2 (Pins 25, 18/Pins 24, 17):
Bootstrapped Phase Detector. This pin is internally terminated to SGND Supplies to the Top Side Floating Drivers. Capacitors are with 50kΩ. The phase-locked loop will force the rising top connected between the boost and switch pins and Schot- gate signal of controller 1 to be synchronized with the tky diodes are tied between the boost and INTVCC pins. rising edge of the PLLIN signal. Voltage swing at the boost pins is from INTVCC to (VIN +
FCB (Pin 7/Pin 4):
Forced Continuous Control Input. This INTVCC). input acts on both controllers and is normally used to
SW1, SW2 (Pins 26, 17/Pins 25, 15):
Switch Node regulate a secondary winding. Pulling this pin below 0.8V Connections to Inductors. Voltage swing at these pins is will force continuous synchronous operation. Do not from a Schottky diode (external) voltage drop below leave this pin floating. ground to VIN.
ITH1, ITH2 (Pins 8, 11/Pins 5, 8):
Error Amplifier Outputs
TG1, TG2 (Pins 27, 16/Pins 26, 14):
High Current Gate and Switching Regulator Compensation Points. Each as- Drives for Top N-Channel MOSFETs. These are the outputs sociated channels’ current comparator trip point increases of floating drivers with a voltage swing equal to INTVCC – with this control voltage. 0.5V superimposed on the switch node voltage SW.
SGND (Pin 9/Pin 6):
Small Signal Ground. Common
PGOOD (Pin 28/Pin 27):
Open-Drain Logic Output. PGOOD to both controllers; must be routed separately from is pulled to ground when the voltage on either VOSENSE pin high current grounds to the common (–) terminals is not within ±7.5% of its set point. of the COUT capacitors.
Exposed Pad (Pin 33, UH Package):
Signal Ground. Must
3.3VOUT (Pin 10/Pin 7):
Linear Regulator Output. be soldered to the PCB ground for electrical contact and Capable of supplying 10mA DC with peak currents as optimum thermal performance. high as 50mA. 3727lx1fa 8